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USB superspeed peripherals Forum Discussions

jnagy
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Level 3
25 replies posted 25 sign-ins 10 replies posted

I am using the CYUSB3014 connected to a FPGA via a synchronous FIFO where the FPGA is the master and I want to configure FLAGA on my GPIF interface to always show the watermark status of thread 0. I want the watermark to set if there is 15372 or more bytes inside the buffer however I cannot find the correct value for the CyU3PGpifSocketConfigure function.

I have configured the firmware DMA buffers to 16KB (16 * 1024 bytes) where all of the space except 16 bytes is available for UVC data. I am using the DMA config's DMA header of 12 bytes for UVC header and footer of 4 bytes to maintain a data size that is a multiple of 16 bytes). I have also configured the flag settings in GPIF II Designer and ensured it is set to correct polarity, GPIO and thread. 

My use case is an external master synchronous slave FIFO which is the same as example (1) from section 9.3 of AN65974.  I am using a 32-bit wide bus so the number of data words that can be written is (16384 - 12 - 4) - 15372 = 996 bytes = 249 32-bit words. Using this value in the formula gives:

 

249 = watermark * (32/32) - 4
249 = watermark - 4
253 = watermark

 

However when I set a watermark value of 253 in CyU3PGpifSocketConfigure I see the flag being continuously asserted even when no data is fed to it. There is a small blip where it is unasserted but after that it continues being asserted. I have included an image of the ILA capture which shows the blip when the FIFO is being fed no data. I am using the following to configure the watermark

 

CyU3PGpifSocketConfigure(
        0,                          /* Thread to configure */
        CY_FX_EP_VIDEO_PROD_SOCKET, /* Socket to associate with this thread */
        253,                        /* Watermark value in 4-byte words */
        CyTrue,                     /* Whether watermark flag should be set when above watermark value */
        8                           /* Burst size (X * 2 words) */
);

 

 Help on finding out why my watermark isn't being asserted how I expect would be greatly appreciated.

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1 Solution
Rashi_Vatsa
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5 likes given 500 solutions authored 1000 replies posted

Hello,

Please find my comments below:

However when I set a watermark value of 253 in CyU3PGpifSocketConfigure I see the flag being continuously asserted even when no data is fed to it.

>> If the flag  (Thread0_DMA_watermark) is configured as Active LOW, the flag will be HIGH when the DMA buffer is ready (i.e. ready to get the data from FPGA), and will be asserted LOW based on the watermark i.e. it will expect data for 253 clock cycles after flag asserting low.

Please confirm if FPGA is monitoring  watermark flag only for stopping the data transfer and not for starting the data transfer and if the watermark is configured as Active LOW

Also, let us know why burst size is used as 8. We suggest to try with these settings

CyU3PGpifSocketConfigure (0,CY_U3P_PIB_SOCKET,253,CyFalse,1);

Regards,
Rashi

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Rashi_Vatsa
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5 likes given 500 solutions authored 1000 replies posted

Hello,

Please find my comments below:

However when I set a watermark value of 253 in CyU3PGpifSocketConfigure I see the flag being continuously asserted even when no data is fed to it.

>> If the flag  (Thread0_DMA_watermark) is configured as Active LOW, the flag will be HIGH when the DMA buffer is ready (i.e. ready to get the data from FPGA), and will be asserted LOW based on the watermark i.e. it will expect data for 253 clock cycles after flag asserting low.

Please confirm if FPGA is monitoring  watermark flag only for stopping the data transfer and not for starting the data transfer and if the watermark is configured as Active LOW

Also, let us know why burst size is used as 8. We suggest to try with these settings

CyU3PGpifSocketConfigure (0,CY_U3P_PIB_SOCKET,253,CyFalse,1);

Regards,
Rashi
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How does clock cycles enter into it? I thought the watermark was based only on how full the FIFO is. Can you explain “it will expect data for 253 clock cycles after flag asserting low” a bit more in depth?

My firmware uses writes in bursts of 16 packets and I was led to believe that this was the burst size for writing over 2. I will try your suggested settings.

Edit: Your settings seem to have done the trick and it works as expected now. Can you explain how changing the last 2 parameters solve the problem?

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Rashi_Vatsa
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5 likes given 500 solutions authored 1000 replies posted

Hello,

Glad to hear that the issue is resolved!

How does clock cycles enter into it? I thought the watermark was based only on how full the FIFO is. Can you explain “it will expect data for 253 clock cycles after flag asserting low” a bit more in depth?

>> As per your requirement, watermark flag should be asserted when 15372 bytes are received by FX3. In that case, watermark value is 253 i.e. the watermark flag will be asserted when 253*4 (4 bytes per clock are sampled as GPIF bus width is 32 bits) = 996 bytes are left to be written to FX3.

Edit: Your settings seem to have done the trick and it works as expected now. Can you explain how changing the last 2 parameters solve the problem?

>> flagOnData parameter will decide when the flag should be asserted. It should be set to false when the flag is to be set when the socket contains less data than the watermark.

for last paramater "burst", please refer to section 9.5 of AN65974

Regards,
Rashi
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