As I know basically USB3 is using the 1024 bytes one packet to transceiver the data between host application and CYUSB3KIT-003.
So currently I have no problem to receive 1024 times data transfer,
above these transfer is working good.
But, in my case, that the transfer of data is not 1024 times.
Actually my case is
as you can see, I need that slavefifo firmware with non 1024 multiple packet.
Would you let me know how do I implement the non 1024 multiple transfer slavefifo firmware?
Please let me know what am I suppose to do what I want to implement the slavefifo firmware can handle the length of 5038848 (2592*1944).
I suppose you have already referred AN65974. This projet supports all kind of data transfer (full packet/short packet). In your case, the data is not a multiple of 1024, so at the end of the data you just need to commit the partial buffer and you are good to go. So, at the end of 5038848 , the FPGA needs to assert a signal to indicate the FX3 that the transfer is complete. Once the FX3 detects this, the FX3 need to commit the partial buffer. So, you can add a condition in your state machine to identify the end of transfer, and then do a (Commit+IN_data). If you do (Commit+IN_data), then the partial buffer will get committed.
Can I make a case for this?
In " So, at the end of 5038848 ," you answer, It means that I have to count the number of data in the FPGA, in other word, also there is no flexible to the length of data transfer if I once set the length of transfer by using Xferdata(buf,length). I want to have the flexible to the length of transfer data.
For example if I want to get 1921x3952 bytes, and follow by I want get 8329x2911. I can show you as the sudo code this activity like this.
Can The FX3 works like that?
If can, please let me know, I want to know more how to do.
1) In case of short packet (not multiple of EP size). The FPGA is suppose to indicate the FX3 so that the FX3 commits the short buffer.
2) In case the data is multiple of max EP size (and not a multiple of DMA buffer size), the FPGA should indicate the FX3 so that the FX3 does commit + ZLP. ZLP is required for the USB host to understand that the transfer ended. In case of short packet, ZLP is not needed.
Yes, the FPGA should know when you assert which signal. It needs to have a count of data so that it knows when to assert signal for (1), and when to assert control signal for (2).