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USB superspeed peripherals

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I would like to get clarified some ambiguities in the GPIF 2 Designer Guide, regarding "special function" signals OE, WE, DLE, DACK and DRQ.

Their primary documentation, is in User Guide, on page 16, and there's also discussion on page 51, and also in AN87216 p13.

1. Combining info on all those pages, so far as I can tell, OE and WE do the same thing. If this is not true, then what do they do different?

2a. For signal DLE, UG-p16 says that DLE is used to latch the data into the input stage. If that's the case, and since it's on the same pin as WE, perhaps that's supposed to be the difference between WE and OE?  GPIO 18 (WE/DLE) performs input data capture and output driver enable/disable, while GPIO_19 performs only driver disable?

2b. But that supposition is contradicted by UG-p51 and AN87216 p13 where we learn that DLE is not for capturing the input data per se, but rather just to extend the input data hold time. So which is it? Data capture, or extending input data hold time?

2c. And what is the relationship of WE and/or DLE to the IN_DATA action, which seems able to capture input data based on some other input signals altogether?

3. DRQ and DACK: Docs describe DRQ as DMA Request (from FX3 to external device), which seems fine. But then docs describe DACK (DMA Acknowledge) as "an input that is used to control the behavior of the DRQ signal".  This explanation seems nonsensical to me.

The purpose of DACK is surely not to control DRQ per se.  DRQ and DACK surely work together to operate an FX3-side state machine, and interact with the external-device-side's DMA facility, in order for the FX3 to fetch data from, or send data to, the external device.

3a. It's not clear whether the DRQ/DACK signals relate directly to FX3 internal DMA apparatus, or are a separate mechanism, perhaps intended to work with the DMA facility of the external device?

3b. It's not clear how DRQ/DACK do or don't relate to DMAn_Ready and ...Watermark signals.

3c. It's not clear whether DRQ/DACK operate separately from the GPIF state machine. If they require the GPIF state machine, then what is the significance of these signals being on specific pins, since presumably the GPIF state machine could implement these functions on any GPIOs?

There are some other ambiguities and gaps, but let's start with these please.  -- Graham

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