GPIF slave FIFO 5Bit Address

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wyw
Level 3
Level 3
25 replies posted 25 sign-ins 10 replies posted

I configured GPIF II as 5 bit slave FIFO by GPIF II Designer,and data width is 32bit,PCLK 100MHz,FLAGA is Current_Thread_DMA_Ready,FLAGB is Current_Thread_DMA_WaterMark and not used.FPGA as master, configure dma buffer size is 512, buffer count is 2 in fx3 firmware, use CY_U3P_PIB_SOCKET_3 as producer, the first 188 bytes of received data is 0, the following data is normal,could you give me some help?

 

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wyw
Level 3
Level 3
25 replies posted 25 sign-ins 10 replies posted

This problem may be caused by the unstable power-on state of the FPGA, resulting in data on the slaveFIFO interface. This problem is solved by delaying the delivery of SLCS signals in my design. 

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AliAsgar
Moderator
Moderator
Moderator
1000 replies posted 250 solutions authored 750 replies posted

Hi,

Is FX3 receiving the data? Are the transfers started based on FlagA?

Could you share with us the interface signals between FPGA and FX3?

Best Regards,
AliAsgar

 

 

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wyw
Level 3
Level 3
25 replies posted 25 sign-ins 10 replies posted

This problem may be caused by the unstable power-on state of the FPGA, resulting in data on the slaveFIFO interface. This problem is solved by delaying the delivery of SLCS signals in my design. 

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