Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

USB superspeed peripherals Forum Discussions

LiWe_3614716
Level 1
Level 1
First like received

Greetings y'all,

I have a platform with a Xilinx FPGA.

The interface to FX3 is based on the 2bit master sync example using 32bit.

(slfifoasync – Asynchronous Slave FIFO)

I am only using it to pass 1 stream of data to PC so only 1 IN bulk endpoint is used.

FX3 firmware and a test pc application is working great.

The PC records 5 seconds of data (some test pattern counter), dumps it to a file and reports average data rate.

Now, I want to extend this solution to have 3 separate streams of data into 3 endpoints.

The FPGA has been modified to output 3 types of patterns in different rates via 3 different threads.

Thread0 (2bit address = 00) outputs data rate of 16KB/sec

Thread1 (2bit address = 01) outputs data rate of 32MB/sec

Thread2 (2bit address = 10) outputs data rate of 125MB/sec

Before changing the FX3 firmware and test app, The correct data pattern is read at the rate of 16KB/sec as I have expected.

Now the only change I make to the firmware is to read thread1.

CyU3PGpifSocketConfigure first argument.

All other settings (Sockets and EP are the same).

Now pc app is geting data at the rate of 32MB/s but the pattern match the one on thread0.

When the firmware is changed to read thread2, data rate measured is 125MB/s but pattern still match thread0.

When I choose other sockets no data is coming out.

Of course I change both CyU3PGpifSocketConfigure second argument as well as the DMA settings.

I thought that sockets are logical entities that could route to any socket (at least in this simple example).

Any thoughts?

Thanks,

Lior.

0 Likes
1 Solution
Hemanth
Moderator
Moderator
Moderator
First like given First question asked 750 replies posted

Hi Lior,

Referring to your first test:

When you changed the first argument of CyU3PGpifSocketConfigure(), you are changing the thread-socket mapping. By default PIB-Thread0 is mapped to Socket0. By only changing the first parameter, say to 1, you are changing the mapping of Thread1 to Socket0 which is not correct.

You can map Thread0 to Logical Sockets 0, 4, 8,...,28 as shown in Figure 4 of AN68829

Similarly, Thread1 can be mapped to Logical Sockets 1, 5, 9,...,29.

This mapping is done using CyU3PGpifSocketConfigure().

(I pointed the app note AN68829 above, just to show the thread-socket mapping. Since you only need 3 separate streams, you need not implement 5-bit mode)

So, in your case, to send the data over Thread1, you will have to assert the address pins on the GPIF interface accordingly as Thread 0/1/2/3.

Please let me know if anything is not clear.

Regards,

Hemanth

Hemanth

View solution in original post

0 Likes
3 Replies
Hemanth
Moderator
Moderator
Moderator
First like given First question asked 750 replies posted

Hi Lior,

Referring to your first test:

When you changed the first argument of CyU3PGpifSocketConfigure(), you are changing the thread-socket mapping. By default PIB-Thread0 is mapped to Socket0. By only changing the first parameter, say to 1, you are changing the mapping of Thread1 to Socket0 which is not correct.

You can map Thread0 to Logical Sockets 0, 4, 8,...,28 as shown in Figure 4 of AN68829

Similarly, Thread1 can be mapped to Logical Sockets 1, 5, 9,...,29.

This mapping is done using CyU3PGpifSocketConfigure().

(I pointed the app note AN68829 above, just to show the thread-socket mapping. Since you only need 3 separate streams, you need not implement 5-bit mode)

So, in your case, to send the data over Thread1, you will have to assert the address pins on the GPIF interface accordingly as Thread 0/1/2/3.

Please let me know if anything is not clear.

Regards,

Hemanth

Hemanth
0 Likes

Hi  Hemanth,

Thank you so much for your prompt reply.

I will check your suggestions next week and let you know the result.

BR,

Lior.

0 Likes

Hi  Hemanth,

Thanks. All is working now.

Best regards,

Lior.