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USB superspeed peripherals

Level 2
Level 2

Hi all,

I am now trying to get the GPIF II of my Fx3s working.

So I would like to try to run the AN82716 example first.

I would need to modify the GPIF II data bus from 32-bit to 16-bit since Fx3s only supports 16-bit data bus.

So I need the GPIF II source project of this example, both the master and slave.

I did found the cyfx file, but when I try to open it in the GPIF II designer, I got the following error.

Error: prj.M00007: Project "C:\Users\hsuan\Documents\GPIF II Designer\master_read_write_sync.cydsn\master_read_write_sync.cyfx" load failed. Error occurred while loading project documents.

1 Solution
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Hi Jay,

Please refer to KBA attached : Configuring EZ-USB® FX3™ GPIF-II DLL - KBA210733

The KBA refers to configuring the DLL block of FX3 (based on desired output PCLK).

The DLL block is configured in the firmware using CyFxApplnSetPibDllParameters(). The configuration is based on output PCLK desired which is mentioned in Table 2 of the above mentioned KBA.

The Output PCLK frequency is based on the pibClock.clkDiv parameter. If the value of clkDiv is 4 or 5 and if the clock_source is SYS_CLK, then Output PCLK >= 80MHz  and if value of clkDiv is greater than 5, Output PCLK < 80MHz and the values of the DLL parameters need to be updated accordingly from the table.

Please find the attached configuration shown in the images for PCLK<80MHz



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