I use FX3S chip. I want to transfer some data PC to FPGA.
I set FX3s Master mode. and I want to use 16 bit AD MUX mode.
And I set DMA type is Auto.
I check FPGA side. Fx3 send Addresses both ALE timing WE timing.
Timing Diagram cycles are seen exactly working. Address send on ALE timing and Data send on WE timing.
ALE timing and WE timing are same data in the FPGA side.
What can I do?
Do you mean that FPGA expects both address and data at the same time? If so, Is it possible for you to change the configuration in FPGA?
I mean use a same bus line both address and data. for example, odd clocks are address in bus line and even clocks are data in bus line.