GPIF II Interface wrong readings for alternating signals

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Ahmedms
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  • I have a CYUSB303X with the GPIF-II interface connected to AD7381-4 ADC. The CYUSB is running the attached AD7381-4_cyfxgpiftousb project.
  • When applying constant voltage on the GPIF pins, I'm able to read them properly at the USB port (on the host PC).
  • When the AD7381-4 digital signals are applied, the readings are always zero (which doesn't correspond to the real data being transmitting). What is the reason for that?

Please see the schematic below:

Ahmedms_0-1672186506581.png

Here are the signals captured by a logic analyzer, they are always read as zeros, if a DC (Zero or 1) is applied on the GPIF input lines, it is read properly at the USB:

Ahmedms_2-1672186656229.png

Here is the USB read:

Ahmedms_3-1672186720941.png

 

 

 

 

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Ahmedms
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Hi Aliasgar, 

After long debugging, I figured out the GPIF-II state machine is wrong.

I altered it a bit and I started capturing data, but still I have some errors that makes the full read of the ADC bits wrong. 

When I attempted to use the below statemachine, I usually find the data is sampled at different States than the one I configured, see how I just IN_DATA in the RD_START state, and in the timing diagram, they are shifted early towards the WAIT and IDLE states.

Ahmedms_1-1675192478968.pngAhmedms_2-1675192492200.png

Ahmedms_0-1675192460130.png

 

Could you please help find the correct state-machine that realizes the following ADC timing diagram?

Ahmedms_0-1675136655843.png

 

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AliAsgar
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Hi,

As CYUSB30XX is used as Synchronous Master mode, DLL should be enabled for the PIB Clock. Please refer to https://community.infineon.com/t5/Knowledge-Base-Articles/Configuring-EZ-USB-FX3-GPIF-II-DLL-KBA2107... KBA for further details.

In the IO Config structure I see that isDQ32bit is set as CyTrue, eventhough according to the GPIF II State machine, data bus width is only 8 bit. Please set isDQ32bit as CyFalse.

Make sure both "sample data from data bus" and "write data to data sink" is checked for action settings for IN_DATA in the GPIF State Machine.

Best Regards,
AliAsgar

 

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Hi 

For the DLL, the link you shared seems a bit old, I found a function: CyU3PPibDllConfigure which is used in the SRAMmaster example to configure the DLL. Following Table 2 in the link you shared, I set the parameters of this function to:

    apiRetStatus = CyU3PPibDllConfigure(CYU3P_PIB_DLL_MASTER,		// dll_mode
										0x46, 						// slave_delay
										CYU3P_PIB_CLK_PHASE_04,		// core_phase
										CYU3P_PIB_CLK_PHASE_00,		// sync_phase
										CYU3P_PIB_CLK_PHASE_00,		// output_phase
										CyTrue);			 		// should_lock

 

I fixed the isDQ32bit value and verified that sample data from bus and write data to data sink are checked.

I still get the same issue.  I also tried multiple phases for the core_phase clock.

 

Could you please check the new attached project and let me know if the DLL is configured properly? 
What else could be causing this issue?


 

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AliAsgar
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Hi,

I replicated your setup at my end, using PWM inputs (50% duty) with varying frequencies from an Arduino UNO as inputs with your firmware. I successfully received data on the USB as per the inputs. I was not able to reproduce the issue at my end.

Please check your hardware connections and try to probe the input signals near CYUSB30XX and check if the signals received near the GPIF are proper.

Best Regards,
AliAsgar

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Hi AliAsgar, 

Sorry I forgot to attach the new code with the DLL
What parameters did you use for the DLL?

    apiRetStatus = CyU3PPibDllConfigure(CYU3P_PIB_DLL_MASTER,		// dll_mode
										0x46, 						// slave_delay
										CYU3P_PIB_CLK_PHASE_04,		// core_phase
										CYU3P_PIB_CLK_PHASE_00,		// sync_phase
										CYU3P_PIB_CLK_PHASE_00,		// output_phase
										CyTrue);			 		// should_lock
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AliAsgar
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Hi,

I copied the DLL values as it is from the SramMaster example. It worked fine. I presume the issue is due to hardware.

Could you let us know the frequency with which ADC is sending out data?

Also try multiple Transfer INs, do all of them show zeros?

Best Regards,
AliAsgar

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Hi AliAsgar, 

Could you please share your project files?

The ADC sends data timed with the PCLK (like a sync FIFO).

I don't believe it's a HW issue because it the HW can recognize DC values applied to the same pins well. I think it's more of a timing issue and I just want to make sure I configured the DLL correctly (from code point of view).

 

Please:

1- Have a look at the attached file in my previous reply and confirm this is the right way (and order) to call the DLL config function

2- Share your project files that worked with the Arduino.

Regards,

Ahmed

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AliAsgar
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Hi Ahmed,

Please find the attached FX3 firmware, Arduino Sketch and Control center output.

Arduino pin 5 (980Hz) -> FX3 DQ1
Arduino pin 3 (480Hz) -> FX3 DQ0
Arduino pin 2(RPI_IN) -> FX3 CTL2

Note that : GPIF II interface clock frequency should lie between 10MHz and 100MHz.

Best Regards,
AliAsgar

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Hi AliAsgar,

Thank you:

  1. I tried the Arduino code you sent, and applied it to my PCB, (exactly at the ADC output pins, the signals passes through the same path the ADC outputs would have passed by), and I was able to capture the correct waveform with the CYUSB30XX chip
  2. I tried your AD7381GpiFToUSB.zip on my board as well, and it shows the same failure as my PCB when I run the adc signals at their true speeds.

I now think the PCB is good, but the CYUSB30XX chip fails to capture data that is synced to PCLK, the Arduino-generated signals are still too slow if compared to the ADC signals that are clocked with PCLK.

Can you answer these questions:

  1. Can the CYUSB30xx recognize data that are clocked in sync with the PCLK? That's what I understood from the examples.
  2. Is there a way to read timing margins though FW? What is the right way to fix the timing and synchronization between Sync, phase, and core clocks such that the data is sampled properly?
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AliAsgar
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Hi,

Please follow the steps mentioned under "2. DLL Configuration" in the given KBA: https://community.infineon.com/t5/Knowledge-Base-Articles/Configuring-EZ-USB-FX3-GPIF-II-DLL-KBA2107... and let us know if this helps to solve your issue.

CYUSB30XX can recognize data that are clocked in sync with the PCLK. Please try all the steps mentioned in the above link.

Best Regards,
AliAsgar

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Ahmedms
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Hi Aliasgar, 

After long debugging, I figured out the GPIF-II state machine is wrong.

I altered it a bit and I started capturing data, but still I have some errors that makes the full read of the ADC bits wrong. 

When I attempted to use the below statemachine, I usually find the data is sampled at different States than the one I configured, see how I just IN_DATA in the RD_START state, and in the timing diagram, they are shifted early towards the WAIT and IDLE states.

Ahmedms_1-1675192478968.pngAhmedms_2-1675192492200.png

Ahmedms_0-1675192460130.png

 

Could you please help find the correct state-machine that realizes the following ADC timing diagram?

Ahmedms_0-1675136655843.png

 

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AliAsgar
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1000 replies posted 250 solutions authored 750 replies posted

Hi,

Could you let us know what is the transition equation from WAIT to IDLE state and what is the trigger for sampling of the signals??

Could you explain the issue you are facing while reading data from ADC ("full read of the ADC bits wrong")?

The timing diagram shown in the GPIF II Designer is error-prone and not reliable. Please do not consider the GPIF II Designer timing diagram as a reference.

Best Regards,
AliAsgar

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Ahmedms
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Hi Aliasgar,

Here is the entire project attached, the timing equation is a GPIO input goes down and DMA is ready:
((DMA_RDY_TH0)&(!RPI_OUT_CYUSB30XX_IN))

In the attached project, I added intermediate states to align the timing as per the timing diagram, which you just said is error-prone. I'm not sure what to use then to simulate the state machine.


For the ADC, This device works as follows:

  • Once the CS pin goes below, the ADC replies back with 16 bits on the 4 SDO_x lines as per the timing diagram I shared above
  • The objective of the CYUSB is: 

    • To generate the CS signal when the DMA is ready, which I think is working fine
    • To capture the 16 bits and send them over USB, which in principle is working, however, the exact timing at which the CYUSB is sampling those bits is my main issue now.
    • How can I guarantee I sample Data_IN at positive edge of PCLK? 

 

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AliAsgar
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Hi,

Please do not modify the GPIF -II state machine as per the timing diagram provided in the GPIF-II Designer application. The timing diagram of the GPIF-II Designer application is not reliable and needs to be ignored. The GPIF II state machine can remain the way it was before (no need for intermediate states).

Please probe the GPIF lines using a logic analyser and check whether any issue is seen. Please share the logic traces with us in such a case for analysis.

Active Clock Edge is configured to be positive in the interface configuration for the GPIF-II designer. Hence, the data will be sampled at the positive edge of the clock.

Best Regards,
AliAsgar

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