Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

USB superspeed peripherals

Level 1
First reply posted First question asked First like given
Level 1



FX3 datasheet contains GPIF II timing diagram for asynchronous DDR mode. However, there is no any additional information about how to use this mode. It is also unclear how to configure this mode in GPIF II Designer.


The API has only one thing that has relation to DDR -- DDR_MODE flag in GPIF_CONFIG register. Documentation says DDR_MODE flag "Select 2X clock as the core clock". That's all.


My guess is that setting DDR_MODE and DLE_PRESENT will allow for latching of DQ lines on every (both rising and falling) edge of CTL[1].


Is my understanding correct? Could you please clarify.


Thank you.

1 Reply
Not applicable

In Asynchronous DDR_MODE, the input data latches are two sets – one is enabled on the rise edge of DLE and the other on the fall edge of DLE. The data from these pass through a mux which selects one path based on which latch is closed. One latch is open during DLE high time and the other during DLE low time. The Mux selects the output of the closed Latch as Input data.