Flags of FX3

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MaXi_1246331
Level 4
Level 4
50 replies posted 25 replies posted 10 replies posted

I develop my FX3 firmare based on AN65974 "Designing with the EZ-USB FX3 Slave FIFO Interface".I have question on how to set the flags in FX3?

Is it set at GPIF II Designer software? In my design at the GUI of the software:GPIO21(FlAGA) is set as the Thread_0_DMA_READY flag.I choose active low. Does this mean GPIO21 correspond to P-Port0. It presents a low level if the P-port is not full? In the GUI I do not choose the Thread_0_DMA_WaterMark. It means I forbid the use of partial flag for this P-port?

Besides the GPIF II Designer GUI, I find the following in the firmware codes: CyU3PGpifSocketConfigure (0,CY_U3P_PIB_SOCKET_0,4,CyFalse,1);

This means if the P-port 0 contains less than 16 bytes the partial flag will be set to active.

Does the GPIF II Designer GUI setting and CyU3PGpifSocketConfigure setting in the firmware conflicts with each other? Which setting will prevail?

Thread_0_DMA_READY means not empty or not full?

Thank you.

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1 Solution

U2P - USB is Producer and P-Port is consumer. The external processor reads the data from P_Port. Hence, it will be emptied. So this empty flag. The other one (P2U) is Full Flag.

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3 Replies
KandlaguntaR_36
Moderator
Moderator
Moderator
25 solutions authored 10 solutions authored 5 solutions authored

In order to prevent the data overflow or underflow, the external processor should know when the buffer is full (writing case) or empty(reading case). Flags are used for this purpose.

There is a finite delay present between the point at which the buffers inside the FX3 become full/empty and actual assertion of flags (for example - Thread_0_DMA_READY ). The delay is different for different flags as mentioned in table 4 of AN65974.

Hence, there is a possibility that by the time the external processor sees the flag,it might have send an extra bytes to GPIF II (assume external processor is writing to FX3 GPIF II) due to the delay in assertion of flag.

This is where the partial flags coming into the picture. This flag should be configured in such a way that the external processor should know      how many cycles it can read/write the data from/to the GPIF.

i.e the number of bytes that the external processor can read/write from/to the GPIF should be known to the external processor and stop the      data transfer after the count. Later wait for de-assertion of the watermark or ready flag then do the data transfer.

To use water mark flags, you must configure them in GPIF Designer and set the water mark value using the API CyU3PGpifSocketConfigure. Note that we cannot set the value in the GPIF designer, hence we must use this API. Hence, we must configure the water mark flag in GPIF II designer and use this API to set water mark value.

Go through the section 8.2, 8.3 and 8.4 to understand this.

You may go through this thread - Re: FX3 Flag polarity and using partial flags

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For U2P transfer Thread_0_DMA_READY is no_empty flag? For P2U transfer Thread_0_DMA_READY is no_FULL flag?

发自我的小米手机

在 srdr <community-manager@cypress.com>,2018年12月20日 下午10:43写道:

<http://www.cypress.com>

Cypress Developer Community <https://community.cypress.com/?et=watches.email.thread>

Flags of FX3

reply from srdr<https://community.cypress.com/people/srdr?et=watches.email.thread> in USB Superspeed Peripherals - View the full discussion<https://community.cypress.com/message/182331?et=watches.email.thread#182331>

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U2P - USB is Producer and P-Port is consumer. The external processor reads the data from P_Port. Hence, it will be emptied. So this empty flag. The other one (P2U) is Full Flag.

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