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USB superspeed peripherals Forum Discussions

Anuj_shanbhag
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Hello, I have created  a Interface between Xilinx FPGA and CYUSB3014 FX3 controller. We are running in slave FIFO 32 bit data mode. We are transmitting  a packet size of 32KB as of now from the FPGA. We want to now increase the payload to 64KB. What configurations in the source code needs to be changed on the controller side?

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Hello,

If the data written by FPGA is not read by USB host then the maximum buffer that can be written will be equal to the DMA buffer size associated with the DMA channel. Increasing the DMA buffer size associated with PIB to UIB channel will help. 

Please note that the DMA buffer area in the default memory map of FX3 (512 KB RAM) is 224 KB so the total DMA buffers used by the firmware should not exceed it.  Refer  Modifying the Default Memory Map in FX3, CX3, FX3S... - Infineon Developer Community  .

Also, a single DMA buffer used on FX3 can have a maximum size of 65520 bytes

Regards,
Rashi

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Rashi_Vatsa
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Hello,

Please confirm if you have referred to this app note https://www.infineon.com/dgdl/Infineon-AN65974_Designing_with_the_EZ-USB_FX3_Slave_FIFO_Interface-Ap...

STREAM IN and STREAM OUT conditions will allow to send/receive data streams. Please let me know if I misunderstood the question

Regards,
Rashi
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Yes. I have referred to the same document and using stream in and stream out. But the FX3 controller is indicating through flaga that the Buffer is full when it reaches 32KB. How to calculate the maximum data payload you can transfer in one go?

 

Regards,

Anuj

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Hello,

If the data written by FPGA is not read by USB host then the maximum buffer that can be written will be equal to the DMA buffer size associated with the DMA channel. Increasing the DMA buffer size associated with PIB to UIB channel will help. 

Please note that the DMA buffer area in the default memory map of FX3 (512 KB RAM) is 224 KB so the total DMA buffers used by the firmware should not exceed it.  Refer  Modifying the Default Memory Map in FX3, CX3, FX3S... - Infineon Developer Community  .

Also, a single DMA buffer used on FX3 can have a maximum size of 65520 bytes

Regards,
Rashi

Thanks for the quick reply. I will look into this. I had one more query. As you mentioned the buffer for DMA is 224KB. In the FX3 you can have four threads accessible through two address pins. In my current implementation, two of these will be used. One for stream in and one for stream out. So it will be divided equally among it?

Regards,

Anuj

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Hello Anuj,

As per your response, two DMA channels will be needed. Each DMA channel will have DMA Buffers associated with them. So, as the total memory allocated for DMA is 224 KB in the default memory map, the DMA buffers will allocated from the 224 KB for the DMA channels created in the firmware.

Please refer to this KBA  DMA Buffer Count - KBA218339 - Infineon Developer Community  

Regards,
Rashi