FX3 to FPGA via GPIF II Interface

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poas_4520791
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Hi,

I have to  transfer data from FX3 to FPGA  using GPIF II interface.I'm using the firmware that is in  AN65974 and i will give data through control center.But i'm able to receive only starting 2 bytes,the remaining bytes are missing,as shown in below snapshot.What may be the reason for this,kindly anyone  let me know the issue. 2.PNG

Regards,

Aswini

1 Solution

Hello Aswini,

I tried to reproduce at my end.

I programmed the FX3 with default firmware and checked the flags before and after transfer (without reading it on GPIF side)

interface_slavefifo.PNG

These are the traces i got with proper PCLK - initially low and gets high when some data is transferred. Flags C goes low again when DMA buffer is FULL

flags.PNG

I also observed that if PCLK is not given properly these flags misbehave.  Trace with flags without proper PCLK and before data transfer .

without_clock.PNG

Initially before transfer both flags will be low as mentioned in state machine. So before transferring you should get both flags low.

gpifff.PNG

Regards,

Rashi

Regards,
Rashi

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42 Replies

Hello Aswini,

I tried to reproduce at my end.

I programmed the FX3 with default firmware and checked the flags before and after transfer (without reading it on GPIF side)

interface_slavefifo.PNG

These are the traces i got with proper PCLK - initially low and gets high when some data is transferred. Flags C goes low again when DMA buffer is FULL

flags.PNG

I also observed that if PCLK is not given properly these flags misbehave.  Trace with flags without proper PCLK and before data transfer .

without_clock.PNG

Initially before transfer both flags will be low as mentioned in state machine. So before transferring you should get both flags low.

gpifff.PNG

Regards,

Rashi

Regards,
Rashi
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Hello,

Based on your traces i'm thinking that the problem is with PCLK(FPGA side).So,can you send me the snapshot of  your FPGA block design,so that i will compare it with my FPGA design(mainly clock connection).

And also please send  me the FPGA files which you are using now.

Regards,

Aswini

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Hi Aswini,

I didn't check this with FPGA but with another CYUSB3KIT-003 (Master) .

I tested this with two  CYUSB3KIT-003, one as Master (drives PCLK) and other as Slave  and checked the flags status. I have just connected GPIO 16 i.e. PCLK of both kits using jumper wires

Regards,

Rashi

Regards,
Rashi
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