I'm sorry but I don't see that anywhere in section 4.2 of AN75705. At best it defines GPIF II as part of the PIB, but makes no mention of P-Port. Did you link the correct AppNote?
4.2 GPIF II
The high-performance GPIF II (a part of the processor interface block (PIB)) enables functionality similar to, but more
advanced than, FX2LP's GPIF and Slave FIFO interfaces. GPIF II is a programmable state machine that enables a
flexible interface running on its own high-speed clock, autonomous to the Arm9. GPIF II may either function as a master
or slave in industry-standard or proprietary interfaces. Both parallel and serial interfaces may be implemented with
GPIF II.
The key features of GPIF II are:
▪ Functions as master or slave.
▪ Provides 256 programmable states.
▪ Supports 8-bit, 16-bit, 24-bit, and 32-bit parallel data bus.
▪ Supports interface frequencies up to 100 MHz.
▪ Supports 14 configurable I/O pins (to function as control signals) when a 32- bit data bus is used. Control pins can
be input, output, or bidirectional.
▪ Supports 16 control I/O pins when a 16/8 data bus is used. Control pins can be input, output, or bi-directional.
Cypress’s GPIF II Designer Tool enables fast development of GPIF II state machines and includes examples for
common interfaces. The GPIF II Designer Tool is available with the EZ-USB FX3 SDK installation.
A popular implementation of GPIF II is a synchronous Slave FIFO interface, used in many FPGA interfaces. For details
on the synchronous Slave FIFO interface, refer to AN65974 - Designing with the EZ-USB FX3 Slave FIFO Interface.
