FX3 synchronous slave FIFO read PCLK active edge

[MaXi_1246331]

The datasheet of FX3 says for synchronous slave FIFO read, the data becomes valid in tco after the rising edge PCLK (from FPGA to FX3). I find the data becomes valid in tco after the falling edge PCLK, I draw this conclusion from 2 sources. 1) The captured FPGA internal signal

2) The PCLK and data signal captured at the PCB, from FPGA to FX3, as follows. The blue signal is the least significant data bit.

I guess FX3 devices may be updated and the document may not be updated, leading to the difference between description and actual behavior of the devices. Is my understanding correct?