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USB superspeed peripherals Forum Discussions

Rakesh
Level 3
Level 3
25 replies posted 10 questions asked 50 sign-ins

Hello infineon team,

I am doing  a slaveFIFO implementation in FX3. Intially Flag A and B are in high state when FPGA started  write process ,  after writing some bytes Flag A becomes LOW. but Flag B is in high state only. when probing the Flag A it is continuously toggling but Flag B is not toggling.

My buffer size=36848 Bytes     &        Buffer count=6

i am using current thread flag so Flag A = current thread DMA ready and Flag B = current thread watermark value. my watermark value is 10.  address is always 0.

please guide us in what step we are doing mistake. why Flag B is always in HIGH state?

Note: The gpifCONFIG.h file used in this project is already working fine in another FPGA project. 

 

Thanks and regards, 

rakesh

@AliAsgar @Hemanth @JayakrishnaT_76 

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9 Replies
AliAsgar
Moderator
Moderator
Moderator
250 solutions authored 750 replies posted 50 likes received

Hi Rakesh,

1. Is forceful committing of DMA buffer being done in your application. Note that watermark flags will not be reflecting the status if DMA buffer is committed forcefully.

2. Could you share with us the GPIF state machine and the interface signals probed near FX3.

3. "The gpifCONFIG.h file used in this project is already working fine in another FPGA project." Can you let us know the differences in the other FPGA project with respect to the current one?

4. Do you have the feature of reading data from FX3 to FPGA, if yes, can you test if watermark flag is working in that case?

Best Regards,
AliAsgar

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Hi aliasgar,

Thanks for your reply.

1. Is forceful committing of DMA buffer being done in your application. Note that watermark flags will not be reflecting the status if DMA buffer is committed forceful.

     >> I am not clear about forceful commit can you elaborate it. we have done commit buffer only inside dmacallback. apart from that we didnt do any commits. 

Rakesh_0-1674824659376.png

2. Could you share with us the GPIF state machine and the interface signals probed near FX3.

     >>> attached below.

3. "The gpifCONFIG.h file used in this project is already working fine in another FPGA project." Can you let us know the differences in the other FPGA project with respect to the current one?

     >>>Both are different FPGA and operating voltages are different. previous one is 3.3V and new one is 1.8 V

4. Do you have the feature of reading data from FX3 to FPGA, if yes, can you test if watermark flag is working in that case?

          >>> No we don't have that feature in our project.

Thanks and regards,

Rakesh 

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Rakesh
Level 3
Level 3
25 replies posted 10 questions asked 50 sign-ins

Hi aliasgar ,

can you please provide a update on this issue ? we need support for solving this issue.

Thanks and regards, 

Rakesh 

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AliAsgar
Moderator
Moderator
Moderator
250 solutions authored 750 replies posted 50 likes received

Hi Rakesh, 

From the timing diagram I see that SLWR remains asserted even after Flag A gets asserted (Full). This is not expected. Please confirm if the FPGA is programmed appropriately.

Please use different GPIO for watermark flag and check if the flags work properly.

Please let me know where is the GpifSocketConfigure API used in the firmware?

Best Regards,
AliAsgar

 

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Hi aliasgar, 

Thanks for your reply. 

I will update you regarding FPGA once i confirmed the my team.  But i have doubt , as per my understanding FLAG B should become LOW before FLAG A since FLAG B is watermark value . but in my case it is not happened could you explain why this behavior happens.

Thanks and regards,

Rakesh

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Rakesh
Level 3
Level 3
25 replies posted 10 questions asked 50 sign-ins

Hi aliasgar,

I am unable change GPIO  watermark FLAG because other GPIO pins available in GPIF II designer tool is used for SPI related purpose. but i have manually override the watermark GPIO FLAG and tried toggling the pin it is working fine. so no problem with GPIO pin.

i configure the GpifSocketConfigure API as below steps

UVCApplnInit()

{

    CyU3PPibInit();

    I2cinit();

    CyU3PGpifLoad();

    CyU3PGpifSocketConfigure();

    CyU3PGpifSMStart (); 

    CyU3PGpifSMControl(CyTrue);

   CyU3PGpifRegisterCallback(CyCx3GpifCB);

}

/* After the FPGA is booted and  when application is started*/ 

{

CyU3PGpifSMSwitch(257, RESET,257, CyFalse, 2);

CyU3PThreadSleep(10);
CyU3PGpifSMControl(CyFalse);

 }

can you give us a comment on above thread regarding FPGA operating voltages 3.3V  and 1.8V. will it impact slaveFIFO interface in FX3 ?

please guide us in resolving our mistake .

Thanks and regards,

Rakesh

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AliAsgar
Moderator
Moderator
Moderator
250 solutions authored 750 replies posted 50 likes received

Hi Rakesh,

Can you let us know what parameters were passed to the GpifSocketConfigure API.

Regards,
AliAsgar

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Hi aliasgar,

CyU3PGpifSocketConfigure (0,CY_U3P_PIB_SOCKET_0,10,CyFalse,1);

Regards,

Rakesh

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AliAsgar
Moderator
Moderator
Moderator
250 solutions authored 750 replies posted 50 likes received

Hi Rakesh,

The watermark flag behavior you see is not expected. Watermark flag should have gone low few cycles before full flag. This issue needs to be debugged. 

Let us know the amount of data being sent before asserting PKTEND signal?

Best Regards,
AliAsgar

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