We use the FX3 slave FIFO interface between USB and an FPGA device as described in AN65974 and observe that after ending the software it is not longer possible to communicate if the USB is meanwhile disconnected and reconnected or the PC powered down. It is still possible to read an EEPROM via endpoint 0 and I2C, but the 32-bit synchronous slave FIFO interface of GPIF2 in automatic mode does not longer work. I tried to use VBATT instead VUSB as primary supply by using CyU3PUsbVBattEnable, but it did not help. It is necessary to switch the power of the device off and on before it works again.
Do you have any suggestions or hints?
