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USB superspeed peripherals

wowi
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We use the FX3 slave FIFO interface between USB and an FPGA device as described in AN65974  and observe that after ending the software it is not longer possible to communicate if the USB is meanwhile disconnected and reconnected or the PC powered down. It is still possible to read an EEPROM via endpoint 0 and I2C, but the 32-bit synchronous slave FIFO interface of GPIF2 in automatic mode does not longer work. I tried to use VBATT instead VUSB as primary supply by using CyU3PUsbVBattEnable, but it did not help. It is necessary to switch the power of the device off and on before it works again.

Do you have any suggestions or hints?

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AliAsgar
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Hi,

From your question I have understood that, when a USB disconnection and reconnection occurs, or if the PC powers down, FX3 fails to communicate with the host. Only power cycle of the device, makes it work. Is my understanding correct? If not please explain the issue a bit more clearly.

1. Is the device self powered? Is any VBatt connected to the device?

2. Could you try programming the device with the default USBBulkSrcSink firmware, and just check if the issue is seen there as well (Bulk transfers after USB disconnection and reconnection).

Best Regards,
AliAsgar

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wowi
Level 2
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Level 2

Hi AliAsgar,

1. Yes, the device is self powered. VBatt is present and it works as well using VUSB as VBATT  as the primary supply using CyU3PUsbVBattEnable.

After closing the software and disconnecting and reconnecting the USB and restarting the software, I can communicate with the FX3 using endpoint 0 and I can read the EEPROM via I2C and see that the FPGA firmware is loaded and the GPIF II is switched to slave FIFO mode. But the communication using the slave FIFO interface does not work anymore. The GPIF II is in auto mode, i.e. it communicates directly with the USB.

2. It seems to work writing some data to the FPGA, but then I expect data sent from the FPGA through the GPIF II to the host and this fails.

Best regards,

Wowi

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AliAsgar
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Hi Wowi,

I suspect that the issue maybe due to the errata 2 mentioned in the datasheet. 

1. Is FX3 is USB boot mode?

2. Does the FX3 enumerate properly when PC is reset or USB disconnection reconnection occurs?

3. Could you try programming FX3 with USBBulkSrcSink firmware and let me know if the transfers happen properly in the control center when PC is reset or USB disconnection reconnection happens.

Best Regards,
AliAsgar

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wowi
Level 2
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Level 2

Hi AliAsgar,

it is not the errata 2.

After USB disconnection and reconnection, the FX3 enumerates properly.

Communication via endpoint 0 is ok, I can read the EEPROM. I can see that the FPGA firmware is already loaded and the GPIF II switched to slave FIFO mode.

But bulk transfers do not work any more. Usually I write 16 bytes to the FPGA via GPIF II and then read 16 bytes back from the FPGA to get 4 registers. Writing of 16 bytes works, but reading then fails with a Timeout error. I can also write some more bytes, but when trying to write more than 160 bytes, this fails also with timeout error.

Best regards,

Wowi

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AliAsgar
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Hi Wowi,

I understood that the issue is not related to errata 2. Write is working fine, but read from FPGA is giving timeout errors. 

Which host application is being used?

I want to narrow down the issue if it is on the GPIF side or on the USB side. For this, can you program FX3 with USBBulkSrcSink firmware and check if the issue is seen during data transfers?

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wowi
Level 2
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Hi AliAsgar,

We use our own software as host application. The FX3 and FPGA is used like in AN84868 and AN65974. Writing to the FPGA works after USB disconnection and reconnection only for up to ten transfers with each 16 bytes, then it fails with timeout error. I assume the data don't get to the FPGA, therefore it does not send a replay and reading fails.

I have programmed the FX3 with USBBulkSrcSink firmware and tested it with the Streamer Example. Here the USB disconnection and reconnection works without problem.

So the issue may be related with the GPIF side?

 

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AliAsgar
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Hi,

Could you check if there are any prod events coming in from the PIB side after USB disconnection/reconnection?

Can you probe the Data/Control lines after USB disconnection/reconnection, when FPGA writes to FX3?

Best Regards,
AliAsgar

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wowi
Level 2
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Hi AliAsgar,

what do you mean with "PIB side"?

We will have to create a debug version of the FPGA firmware to check.

The slave FIFO interface is modified to provide three endpoints, EP1 OUT 0x01,

EP1 IN 0x81, and EP2 IN 0x82. I attach our FX3 firmware source, the ConfigFPGASlaveFifoSync version that uses VBatt.

The FPGA will write to the USB only after it is prompted by data sent from the PC side, so if this fails it will also not respond.

Best regards,

Wowi

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AliAsgar
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Hi,

Could you try calling a CyU3PGpifDisable(CyTrue) API inside the SlFifoApplnStop function?

Can you remove the self power and power it just by using VBUS and check if the issue is seen?

Please share the UART debug prints when the issue is seen.

Best Regards,
AliAsgar

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wowi
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Hi AliAsgar,

thankyou for your answer.

Removing the self power and calling CyU3PGpifDisable(CyTrue) API inside the SlFifoApplnStop did not help up to now.

I cannot see the Uart output, may be you can help me with this problem?

The Tx is connected to GPIO[55] as we use 32 bit GPIF bus width. Must it be explicitely enabled somewhere? The GPIO[53..56] are used first for SPI to program the FPGA, but it should be possible to let the GPIO[55] connected to the Uart Tx.

Can you see something missing for setting the Uart in our firmware code?

Best regards,

Wowi

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AliAsgar
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Hi Wowi,

Are the UART prints never coming? Even during the working case. Is the UART screen completely blank or is atleast any garbage data coming.

When the FX3 the USB disconnection and reconnection happens during bus power, a VBUS_REMOVED USB event comes. You could check whether this USB event is generated on removal of VBUS.

Best Regards,
AliAsgar

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