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Hello,
This question has two parts: partial flag and throughput, they seem strangely interlinked.
I am using the example project 'slfifosync' located in: C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\slavefifo_examples\.
I want to implement a FPGA -> FX3 -> PC link, such that data generated on the FPGA is sent through to the PC, therefore I used this example project as a start. My current implementation:
FPGA: the FPGA writes 1024 Bytes of data (512 x 16bit transfers, on the last word which I transfer I assert nPKEND. PCLK is 50MHz.
The FPGA FSM waits for flag A (the full flag) before starting to write to the FX3. It then writes the 1KB of data, whilst monitoring flag B (the partial flag blue). After completing the first 1KB write, it starts over, and does this until it reads an asserted flag B.
On the oscilloscope, I see that the partial flag (blue) does not assert, whereas the the full flag (flag A, green), does assert. Naturally this results in buffers being overwritten. See image 1:
Image 1:
FX3: the FX3 is setup to auto DMA with the following config,
dmaCfg_auto.size = burst_len*size;//16*1024;
dmaCfg_auto.count = 8;
dmaCfg_auto.prodSckId = CY_FX_PRODUCER_PPORT_SOCKET;
dmaCfg_auto.consSckId = CY_FX_CONSUMER_USB_SOCKET;
dmaCfg_auto.dmaMode = CY_U3P_DMA_MODE_BYTE;
CyU3PDmaChannelSetXfer (&glChHandleSlFifoPtoU,0);//0 is for infinite transfer size
epCfg.enable = CyTrue;
epCfg.epType = CY_U3P_USB_EP_BULK;
epCfg.burstLen = burst_len;//where burst_len = 16 when USB 3
epCfg.streams = 0;
epCfg.pcktSize = size;//where size = 1024 when USB 3
and in cyfxslfifousbdscr.c:
/* Endpoint descriptor for consumer EP */
0x07,
CY_U3P_USB_ENDPNT_DESCR,
CY_FX_EP_CONSUMER,
CY_U3P_USB_EP_BULK,
0x00,0x04,
0x00,
/* Super speed endpoint companion descriptor for consumer EP */
0x06,
CY_U3P_SS_EP_COMPN_DESCR,
16 - 1,//i.e. burst_len -1
0x00,
0x00,0x00
Here is the kicker: when I change
dmaCfg_auto.size = burst_len*size;//16*1024;
to
dmaCfg_auto.size = size;//1024
the partial flag is toggled as expected. Furthermore, the throughput increases from 17600KBps to 89500KBps, measured using Cypress’ C++streamer app. (Packets per TX: 8, Xfers to Queue: 64), see image 2:
Image 2:
I would assume increasing dmaCfg_auto.size would increase the throughput as various posts have made clear, however, as I have explained, the opposite is true.
Although 87MBps is not bad throughput, I know a faster throughput is possible.
What am I doing wrong? Please help.
I also attached the full FX3 project.
Solved! Go to Solution.
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Hi Jurgen,
Instead of using the default example for SlaveFIFOSync, kindly use the AN65974. It has same application and it is fully tested.
If you face the same issue with this example also, kindly post your query here.
Link for the AN 65974:
Thanks & RegardsAbhinav Garg
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Hi,
Default firmware example make use manual DMA channel. Have you modified the firmware to DMA auto channel in both the cases? Yes you are right mostly increasing the DMA buffer size increases the throughput because of less buffer switching but it's not true everytime, there are few combinations which can give better throughput.
Are you getting the weird partial flag behaviour with the attached firmware?
Thanks & Regards
Abhinav
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Hello Abhinav,
- ) the default firmware was altered such that PtoU channel is auto DMA (this stays constant for both cases)
- ) the submitted code does not induce the strange flag behavior. In file 'cyfxslfifosync.c', when you change:
dmaCfg_auto.size = size;
to
dmaCfg_auto.size = burst_len*size;
then the strange partial flag behavior should be present.
Kind regards
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Hello Abhinav,
The fault has not been solved, I meant to show that when you change ‘dmaCfg_auto.size’ from 1024 to 16*1024, the partial flag starts behaving strangely.
Why does this happen? It should increase the throughput significantly but instead causes strange flag behaviour.
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Hi Jurgen,
Instead of using the default example for SlaveFIFOSync, kindly use the AN65974. It has same application and it is fully tested.
If you face the same issue with this example also, kindly post your query here.
Link for the AN 65974:
Thanks & RegardsAbhinav Garg