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USB superspeed peripherals Forum Discussions

user_4067446
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Hi

We are working on a solution that involves i2C communication between the XC7A35T-1FTG256C and FX3 DK and are experiencing problems reading data from the FPGA register.

The issue is that the FX3 does not release the Bus after sending the device address followed by a read bit to the FPGA.

The register we are reading from is 0x40 and has one byte of data. The i2C read code is as follows:

CyU3PReturnStatus_t Status;

CyU3PI2cPreamble_t preamble;

preamble.length    = 3;

preamble.buffer[0] = 0xA2; // i2C write address

preamble.buffer[1] = 0x04;

preamble.buffer[2] = 0xA3; // i2C read address

preamble.ctrlMask  = 0x0002;

uint8_t buffer[] = {0};

Status = CyU3PI2cReceiveBytes(&preamble, (uint8_t *)&buffer, 1, 0);

CheckStatus("I2C_Write", Status);

I have attached an image of the results we get from the signal analyzer.

How do we implement the i2C read transaction in such a way that it releases the bus after sending the read address to the FPGA?

Thanks

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1 Solution
Hemanth
Moderator
Moderator
Moderator
First like given First question asked 750 replies posted

Hi,

Please use CyU3PI2cReceiveBytes() API instead of CyU3PI2cTransmitBytes(). Rest looks good.

For your reference please refer the example in FX3 SDK -

C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\serialif_examples\cyfxusbi2cregmode

Regards,

Hemanth

Hemanth

View solution in original post

3 Replies
Hemanth
Moderator
Moderator
Moderator
First like given First question asked 750 replies posted

Hi,

Please use CyU3PI2cReceiveBytes() API instead of CyU3PI2cTransmitBytes(). Rest looks good.

For your reference please refer the example in FX3 SDK -

C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\serialif_examples\cyfxusbi2cregmode

Regards,

Hemanth

Hemanth

Sorry that was a typo. I have made corrections to the Question.

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Hemanth
Moderator
Moderator
Moderator
First like given First question asked 750 replies posted

Hi,

Fx3 holding SDA line after read address is sent is not expected. Can you please check the register address sent - as I see 0x04 being sent - whereas in the description the intention is to read 0x40.

Regards,

Hemanth

Hemanth
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