FX3 USB-3, Stream In.

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mitexus
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Hello,
We designed FPGA part of the data accusation device. Now we trying transfer the accused data to PC via EZ-USB SX3.
The FPGA signal interface timing diagram shown on the attached   file.  We are planning to use Stream IN approach.  For current application, FIFO buffer is 1024bytes.
According 'AN65974 Designing with the EZ-USB™ FX3 slave FIFO interface', the time taken for the DMA channel to switch to the next buffer is not deterministic, although it is typically a few microseconds. The external master must monitor the flag to determine when the switching is complete and the next buffer has become available for data access.
From the AN65974 the FLAGA and FLAGB timing relation to the SLWR# not clear for Stream IN application. Could you please, provide the documentation and information regarding the FLAGA and FLAGB timing.
Sincerely,
Shamsi

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Rashi_Vatsa
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Hello Shamsi,

The timing of Flag A and Flag B with respect to SLWR can be referred in Figure 4 of AN65974

Please let me know if you are looking for anything specific

Regards,
Rashi

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Rashi_Vatsa
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Hello Shamsi,

The timing of Flag A and Flag B with respect to SLWR can be referred in Figure 4 of AN65974

Please let me know if you are looking for anything specific

Regards,
Rashi
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mitexus
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Hello Rashi,

Thank you for response.

Below my  comments:

We designed FPGA part of the data accusation device. Now we trying transfer the accused data to PC via EZ-USB SX3.
The FPGA signal interface timing diagram shown on the attached   file.  We are planning to use Stream IN approach. 

 

Below some comments and Questions:

  1. The SLWR# length is  1024 Bytes always. Question: How to tell to Sync IN (\Cypress\EZ-USB FX3 SDK\1.3\firmware\slavefifo_examples\slfifosync), that DMA buffer length is 1024 Bytes or Words??
  2. The time interval between consecutive SLWR# is min 42usec always.

     According the  "AN65974 Designing with the EZ-USB™ FX3 slave FIFO interface", the time taken for the DMA channel to switch to the next    buffer  is not deterministic, although it is typically a few microseconds. The external master must monitor the flag to determine when the switching is complete and the next buffer has become available for data access.

     Therefore 42msec is more than enough for switching DMA buffers. Question: Is it correct statement ??

  1. We would like to completely avoid to use Partial Flag FLAG_B . According the  "AN65974 Designing with the EZ-USB™ FX3 slave FIFO interface",  The use of a partial flag may be completely avoided if the external master can implement a counting mechanism and always write an amount of data that equals the size of EZ-USB™ FX3’s DMA buffer. Question: Could we avoid completely Partial Flag FLAG_B ?? Since SLWR# length is  1024 Bytes always.

Sincerely,

Shamsi

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Rashi_Vatsa
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Hello Shamsi,

Please let us know if you are using SX3 or FX3 for your end application. This is because, in your initial description, you have mentioned that "we trying to transfer the accused data to PC via EZ-USB SX3". But later, all the references are for FX3.

Also, please find my comments on your questions below:

1. The DMA buffer size can be configured in firmware for FX3 and the availability of a DMA buffer will be reflected by the status of the ready flag. Please find the code below:

dmaCfg.size  = DMA_BUF_SIZE* size;
    dmaCfg.count = CY_FX_SLFIFO_DMA_BUF_COUNT_U_2_P;
    dmaCfg.prodSckId = CY_FX_PRODUCER_USB_SOCKET;
    dmaCfg.consSckId = CY_FX_CONSUMER_PPORT_SOCKET;
    dmaCfg.dmaMode = CY_U3P_DMA_MODE_BYTE;
    /* Enabling the callback for produce event. */
    dmaCfg.notification = CY_U3P_DMA_CB_PROD_EVENT;
    dmaCfg.cb = CyFxSlFifoUtoPDmaCallback;
    dmaCfg.prodHeader = 0;
    dmaCfg.prodFooter = 0;
    dmaCfg.consHeader = 0;
    dmaCfg.prodAvailCount = 0;

    apiRetStatus = CyU3PDmaChannelCreate (&glChHandleSlFifoUtoP,
            CY_U3P_DMA_TYPE_MANUAL, &dmaCfg);

2. In this question, you have mentioned that the time difference between SLWR# assertion is 42us initially. But later, you asked if 42ms is more than enough for switching DMA buffers. Can you let us know if you mean 42us itself in the second part or did you mean 42ms itself?

3. Yes, it should be ok. The partial flag is intended to signal the master that the buffer is about to be filled. If you are planning to use a DMA buffer of 1024 bytes and if SLWR# is asserted to transfer only 1024 bytes, then you need not be using a partial flag. However, DMA ready flag should be used to start the transfer of data.

Regards,
Rashi
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mitexus
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Hello Rashi,

Thank you for response.

I am using FX-3 board.

My comments below for items:
2. Correct value is 42us.
Question: Is 42usec enough for switching DMA buffers?

Sincerely,
Shamsi

 

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Rashi_Vatsa
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Hello Shamsi,

DMA buffer switching can take around 1 microsecond

Regards,
Rashi
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Thank you, Rashi.

It is good to know, that DMA switching is around 1 microsecond.

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