FX3 UIB power register

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danman
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5 replies posted 5 sign-ins First reply posted

Hello,

the FX3 TRM has chapter 10.9.4 UIB_POWER with register definition.

It specifies RESETN bit as only readable (R) by software. The description says:

```

After setting this bit to 1, firmware will poll and wait for the ‘active’ bit to assert. Reading ‘1’ from
‘resetn’ does not indicate the block is out of reset – this may take some time depending on initializa-
tion tasks and clock frequencies.

```

Is this bit writable from software (firmware) or is it read-only?

Additionally, 10.17.2 UIBIN_POWER has RESETN defined as R/W and description says:

```

This bit is nonfunctional for UIBIN and will not reset anything. Use UIB_POWER register instead.

```

Can you please clarify this discrepancy?

Thank you

1 Solution
Chaithra_p
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50 solutions authored First like given 25 solutions authored

Hello @danman ,

 

Software should have R/W (read and write) permission for RESETN bit of UIB_POWER and only Read permission for ACTIVE bit of UIB_POWER.


We think that these permissions got interchanged.

We appreciate you for pointing this mistake. 

Also, we will update the TRM in the future.

 

 

Thanks & regards,

Chaithra

 

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10 Replies
Chaithra_p
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50 solutions authored First like given 25 solutions authored

Hello @danman ,

 

Software should have R/W (read and write) permission for RESETN bit of UIB_POWER and only Read permission for ACTIVE bit of UIB_POWER.


We think that these permissions got interchanged.

We appreciate you for pointing this mistake. 

Also, we will update the TRM in the future.

 

 

Thanks & regards,

Chaithra

 

danman
Level 1
Level 1
5 replies posted 5 sign-ins First reply posted

There is one more related question I have:

When booting from SPI flash, UIB_POWER is 0x00000000 - then I set the RESETN bit to 1 but ACTIVE never reaches 1.

When booting from USB, UIB_POWER is 0x80000001 - then I set the RESETN bit to 0, ACTIVE goes to 0, set RESETN to 1, ACTIVE goes to 1.

Can this be a bug in the silicon? Is there something else needed for the ACTIVE go to 1?

 

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Chaithra_p
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Hello @danman ,

 

Are you using our DVK or custom board..?

 

Thanks & regards,

Chaithra

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Chaithra_p
Moderator
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Hello @danman ,

 

Can you please try to check this with any other board which you have..? Or if you have FX3 Superspeed Kit(our DVK) you can check with that also (Note: but in Superspeed Kit SPI flash is not there you can check with I2C boot)..?

 

Also, can you check whether your schematic follows AN70707 guideline..?

 

Thanks & regards,

Chaithra

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Hi @Chaithra_p ,

I was following the guideline during designing.

Unfortunately, I don't have any dev board with FX3 - they are pretty expensive - that's why I designed my own.

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Chaithra_p
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Hello,

 

 

Can you please let me know the clock frequencies you have set in the firmware..? that is configuration of CyU3PSysClockConfig_t structure,

 

Thanks & regards,

Chaithra

 

 

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Hello,

these are the clock settings:

  Fx3WriteReg32(FX3_GCTL_CPU_CLK_CFG,
                (1UL << FX3_GCTL_CPU_CLK_CFG_MMIO_DIV_SHIFT) |
                (1UL << FX3_GCTL_CPU_CLK_CFG_DMA_DIV_SHIFT) |
                (3UL << FX3_GCTL_CPU_CLK_CFG_SRC_SHIFT) |
                ((CPU_DIV - 1UL) << FX3_GCTL_CPU_CLK_CFG_CPU_DIV_SHIFT));
  Fx3UtilDelayUs(10);

and:

  Fx3ClearReg32(FX3_GCTL_UIB_CORE_CLK, FX3_GCTL_UIB_CORE_CLK_CLK_EN);
  Fx3UtilDelayUs(5);
  Fx3WriteReg32(FX3_GCTL_UIB_CORE_CLK,
                (2UL << FX3_GCTL_UIB_CORE_CLK_PCLK_SRC_SHIFT) |
                (2UL << FX3_GCTL_UIB_CORE_CLK_EPMCLK_SRC_SHIFT));
  Fx3SetReg32(FX3_GCTL_UIB_CORE_CLK, FX3_GCTL_UIB_CORE_CLK_CLK_EN);
  Fx3UtilDelayUs(5);
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Chaithra_p
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Hello,

 

 

Can you  please give me the definition of the macros which you have used in this..?

 

 

 

Thanks & regards,

Chaithra

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void Fx3UtilDelayUs(uint32_t delay_us)
{
  /* Each loop is 4 instruction cycles */
  uint32_t cnt = delay_us * (CPU_CLK / 4 / 1000000);
  __asm__ __volatile__("1: subs %0,%0,#1; bcs 1b" : "=r"(cnt) : "0"(cnt) : "cc");
}

#define Fx3ReadReg32(a)        (*(volatile uint32_t *)(void*)(a))
#define Fx3WriteReg32(a, v)    ((*(volatile uint32_t *)(void*)(a))=(uint32_t)(v))
#define Fx3SetReg32(a, v)      Fx3WriteReg32((a), Fx3ReadReg32((a)) | (v))
#define Fx3ClearReg32(a, v)    Fx3WriteReg32((a), Fx3ReadReg32((a)) & ~(v))
#define Fx3SetField32(a, f, v) Fx3WriteReg32((a), (Fx3ReadReg32((a)) & ~(a ## _ ## f ## _MASK)) | (((v) << (a ## _ ## f ## _SHIFT)) & (a ## _ ## f ## _MASK)))
#define Fx3GetField32(a, f)    ((Fx3ReadReg32((a)) & (a ## _ ## f ## _MASK)) >> (a ## _ ## f ## _SHIFT))

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