FX3 Slave FIFO Interface DmaChannelCommitBuffer INVALID_SEQUENCE Error

[DaSe_3581511]

Hello,

I am using FX3 with Synchronous Slave FIFO Interface (based on the Cypress FW example “slfifosync”, 32-bit data bus) to perform data read/write accesses from an external processor.

One DMA Channel is configured as CY_U3P_DMA_TYPE_MANUAL with P-port as producer and U-port as consumer. The number of buffers to be allocated for this channel is two. Inside the callback function the DmaChannelCommitBuffer function is called. This DMA Channel is only used to commit short packets.

After data is transferred successful for some time, the DmaChannelCommitBuffer function returns error code 71 (CY_U3P_ERROR_INVALID_SEQUENCE) and the data is not committed. This error may occur when there is a DMA buffer overflow (see KBA218830). I do not understand why a DMA buffer overflow occur, because with Slave FIFO Structure there is no possibility to overflow the FX3 DMA buffers. But it happens, if two short packets are transferred in a very short period of time. The system clock is set to 403.2MHz (KBA85503).

Increasing the number of buffers to be allocated for the channel results in the same error. However, when switching the DMA Channel to CY_U3P_DMA_TYPE_AUTO (also with two reserved buffers) the application runs without error and all data packets are committed.

What would be your suggestions for solving the problem with the manual DMA Channel?

Thank you!

[Rashi_Vatsa]

Hello,

Please let me know if you are using the default slave FIFO example of the SDK and the GPIF state machine

Please confirm if the PIB interrupts registered using CyU3PPibRegisterCallback and are there any PIB interrupts observed.

What is the DMA buffer size used in the firmware? And what is the size of the short packets?

Please let me know if the DMA channel recovers from the error and starts the data transfer again or does it stop completely

Please register for the producer and consumer events, track those events, and print it through UART. Please share the share UART debug prints

1) Register for Prod and cons event

dmaCfg.notification = CY_U3P_DMA_CB_PROD_EVENT | CY_U3P_DMA_CB_CONS_EVENT;

    dmaCfg.cb = CyFxSlFifoPtoUDmaCallback;

2) Track the events

void

CyFxSlFifoPtoUDmaCallback (

        CyU3PDmaChannel   *chHandle,

        CyU3PDmaCbType_t  type,

        CyU3PDmaCBInput_t *input

        )

{

    if (type == CY_U3P_DMA_CB_PROD_EVENT)

    {

        status = CyU3PDmaChannelCommitBuffer (chHandle, input->buffer_p.count, 0);

        if (status != CY_U3P_SUCCESS)

        {

            CyU3PDebugPrint (4, "CyU3PDmaChannelCommitBuffer failed, Error code = %d\n", status);

        }

     else

        /* Increment the counter. */

        glDMARxCountU_to_P++;

    }

    if(type == CY_U3P_DMA_CB_CONS_EVENT)

      {

        glDMATxCountU_to_P++;

      }

}

3) Print the events in the SlFifoAppThread_Entry function

for (;;)

    {

    CyU3PThreadSleep (1000);

        if (glIsApplnActive)

        {

           //  Print the number of buffers received so far from the USB host.

            CyU3PDebugPrint (6, "Data tracker: buffers receivedP_to_U: %d, buffers sentP_to_U: %d.\n",

                    glDMARxCountP_to_U, glDMATxCountP_to_U);

}

But it happens, if two short packets are transferred in a very short period of time.

>> Are these short packets being sent when the DMA channel is CY_U3P_DMA_TYPE_AUTO

Also, share the UART prints which print the producer and consumer events by configuring the channel to CY_U3P_DMA_TYPE_AUTO_SIGNAL

Regards,

Rashi

[DaSe_3581511]

Hello Rashi,

I am not using the default slave FIFO example of the SDK. Added another DMA Channel CY_U3P_DMA_TYPE_AUTO with P-port as producer and U-port as consumer (EP82) for transmitting video data and changed the watermark levels for the P-port sockets.

The DMA buffer size used in the firmware is 1024 Byte. The size of the short packets is variable (from 8 to 20 Bytes). The DMA channel recovers from the error and starts data transfer again.

UART debug prints for the producer and consumer events (DMA type manual):

Data tracker: buffers receivedP_to_U: 747, buffers sentP_to_U: 747

Data tracker: buffers receivedP_to_U: 747, buffers sentP_to_U: 747

Data tracker: buffers receivedP_to_U: 781, buffers sentP_to_U: 781

Data tracker: buffers receivedP_to_U: 781, buffers sentP_to_U: 781

Data tracker: buffers receivedP_to_U: 815, buffers sentP_to_U: 815

Data tracker: buffers receivedP_to_U: 815, buffers sentP_to_U: 815

CyU3PDmaChannelCommitBuffer failed, Error code = 71

CyU3PDmaChannelCommitBuffer failed, Error code = 71

Data tracker: buffers receivedP_to_U: 837, buffers sentP_to_U: 835

Data tracker: buffers receivedP_to_U: 838, buffers sentP_to_U: 836

Data tracker: buffers receivedP_to_U: 838, buffers sentP_to_U: 836

Data tracker: buffers receivedP_to_U: 839, buffers sentP_to_U: 836

Data tracker: buffers receivedP_to_U: 839, buffers sentP_to_U: 836

Data tracker: buffers receivedP_to_U: 882, buffers sentP_to_U: 880

When using CY_U3P_DMA_TYPE_AUTO for this DMA Channel the short packets are sent in the same way.

Regards,

Daniel

[Rashi_Vatsa]

Hello Daniel,

Apologies for the late response.

I am not using the default slave FIFO example of the SDK. Added another DMA Channel CY_U3P_DMA_TYPE_AUTO with P-port as producer and U-port as consumer (EP82) for transmitting video data and changed the watermark levels for the P-port sockets.

>> Okay I understand

UART debug prints for the producer and consumer events (DMA type manual):

>> Please let me know the DMA Buffer Count related to the Manual channel

The "CyU3PDmaChannelCommitBuffer failed, Error code = 71" error is the Invalid Sequence Error, which generally happens when DMA buffers are not consumed as fast as the DMA buffers are written by the master. But this error is not expected when DMA Flags are correctly used for the flow control. Please let me know if the DMA flags are observed by the FPGA/master while starting and stopping the data transfer to FX3. Are the DMA  watermark values kept the same as default firmware?

When using CY_U3P_DMA_TYPE_AUTO for this DMA Channel the short packets are sent in the same way.

>> Do you receive the data properly on the USB host when the Manual channel is changed to AUTO channel?

Regards,

Rashi

[DaSe_3581511]

Hello Rashi,

as my problem is still not completely solved, I try to summarize our previous discussion and answer your questions.

DMA channels:

	DMA Type	ProdSckId	ConsSckId	Buffer Count	Buffer Size	Watermark values
EP82	AUTO	PIB_2	UIB_2	8	1024 * 16	7
EP01	MANUAL	UIB_1	PIB_3	2	1024	0
EP81	MANUAL	PIB_0	UIB_1	2	1024	0

Compared to the default firmware example the DMA watermark values have been changed. As mentioned earlier the DMA Auto channel on EP82 is used for transmitting video data. The DMA Manual channels on EP01 and EP81 are only used for transmitting short packets (max. 300 Byte).

The DMA flags are observed by the FPGA/master while starting and stopping the transfer to the FX3.

With the used communication concept there should be a maximum of two packets for the DMA manual channel on EP81 in a short period of time. Internally I have two paths on EP81. One for synchronous communication (Ping-Pong with EP01) and one asynchronous (one short packet for signaling the application the end of a video transfer on EP82).

The DMA flag latency at the end of each transfer and the DMA buffer switching overhead (550 – 900 ns per buffer) are considered.

Until now I have found two workarounds for my problem with DMA manual channel EP81:

1. When switching the DMA type to Auto data is received properly on the USB host. All the other DMA settings are unchanged (BufferCount=2, Watermark=0) and the short packets are sent in the same way.
2. Decreasing the DMA Buffer Count from 2 to 1. With this configuration data is also received properly on the USB host. Now one short packet must be buffered inside the FPGA/master until the FX3 DMA flags are signaling start of the next transfer. In my opinion this shows that the DMA flags should be observed correctly by the FPGA/master.

Best regards,

Daniel

[Rashi_Vatsa]

Hello Daniel,

Thank you for the details

From the description I understand that the CY_U3P_ERROR_INVALID_SEQUENCE occurs for the EP81 DMA channel which doesn't use the watermark flag (watermark =0).

Internally I have two paths on EP81. One for synchronous communication (Ping-Pong with EP01) and one asynchronous (one short packet for signaling the application the end of a video transfer on EP82).

>> From this I understand that the same  DMA channel (PIB>UIB) associated with EP81 is used to send two types of data 

1) Data in response to data received from EP01 DMA channel

2) To send some data indicating  end of frame of the video transferred on EP82 channel

Is my understanding correct?

Decreasing the DMA Buffer Count from 2 to 1. With this configuration data is also received properly on the USB host.

>> Is the DMA channel  MANUAL in this case?

In my opinion this shows that the DMA flags should be observed correctly by the FPGA/master.

>> Yes, the DMA flags are used for flow control and should be monitored by the master/FPGA to avoid overwriting to DMA buffer.

#PKTEND signal is used to commit the the short packets to the USB socket in the default state machine. Once the DMA buffer will be free i.e. the host consumes the data in the DMA buffer, the DMA READY flag will indicate the same and the FPGA/master is expected to start the next transfer.

When using the DMA channel in MANUAL mode is the DMA READY flag monitored correctly by the FPGA/master. Also let me know how are the DMA flags configured 1)Current thread flag 2) dedicated thread flag

Please let me know if  the AN65974 GPIF state machine modified ?

[DaSe_3581511]

Hello Rashi,

Thank you for the fast response.

Your understanding is correct. The CY_U3P_ERROR_INVALID_SEQUENCE occurs for the EP81 DMA channel which doesn’t use the watermark flag and this DMA channel is used to send two types of data.

When decreasing the DMA Buffer Count from 2 to 1 the DMA Type is MANUAL.

DMA flag configuration:

                FLAG A: Current Thread DMA Watermark

                FLAG B: Current Thread DMA Ready

The AN65974 state machine is not modified.

Regards,

Daniel

[Rashi_Vatsa]

Hello Daniel,

From the last response, I understand that  EP81 channel works fine for following cofigurations

1) EP81 - AUTO channel -2 Buffers

2) EP81 - Manual channel - 1 buffer 

Is that correct?

If yes, for which configuration of EP81 is the error seen. EP81 Manual with 2 buffers works fine (without error)? If this doesn't work can you please share the Slave FIFO interface signals (like flags, SLWR, SLCS, PCLK, PKTEND) when the error is seen.

[DaSe_3581511]

Hello Rashi,

yes, that is correct.

The error is seen for EP81 Manual channel with 2 buffers. However, when the error is seen inside the FX3, I am not able to detect and trigger any error case on the Slave FIFO Interface signals.

I will try again to capture the Slave FIFO Interface signals when the error is seen and share the result in the next few days.

Regards,

Daniel