- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello
I'm referring to the FX3 datasheet reset sequence Figure 29
Please tell me if the following understanding is correct
#1. Is it correct to understand that the power supply stabilization time before releasing the H/W reset is tRPW = 1ms (Min)?
#2. Is it correct to understand that the clock stabilization time before releasing the H/W reset is tRPW = 1ms (Min)?
#3. Assuming SPI boot, the sequence after H/W reset release is recognized as follows.
Correct?
After H / W reset release → PLL lock start → PLL lock complete → IC internal reset release → SPI access start (boot image load start)
Please let us know, if tere are some misunderstanding mentioned above.
Best Regards
Arai
Solved! Go to Solution.
- Labels:
-
USB Superspeed Peripherals
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello Arai san,
#1. Is it correct to understand that the power supply stabilization time before releasing the H/W reset is tRPW = 1ms (Min)?
>> Yes. Please refer to KBA Power Up Sequence for FX3 – KBA221826 - Cypress Developer Community If the Power supply take more time to stabilize than the reset time can be more than 1ms but the minimum time for reset should be 1 ms
2. Is it correct to understand that the clock stabilization time before releasing the H/W reset is tRPW = 1ms (Min)?
>> Yes, as per figure 29 of FX3 datasheet the clock should be stable before releasing the RESET# (RESET - HIGH)
#3. Assuming SPI boot, the sequence after H/W reset release is recognized as follows.
Correct?
After H / W reset release → PLL lock start → PLL lock complete → IC internal reset release → SPI access start (boot image load start)
>> If the minimum reset time is met and clock and all power supplies are stable then the bootloader will start firmware download after tRR time.
Rashi
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello Arai san,
#1. Is it correct to understand that the power supply stabilization time before releasing the H/W reset is tRPW = 1ms (Min)?
>> Yes. Please refer to KBA Power Up Sequence for FX3 – KBA221826 - Cypress Developer Community If the Power supply take more time to stabilize than the reset time can be more than 1ms but the minimum time for reset should be 1 ms
2. Is it correct to understand that the clock stabilization time before releasing the H/W reset is tRPW = 1ms (Min)?
>> Yes, as per figure 29 of FX3 datasheet the clock should be stable before releasing the RESET# (RESET - HIGH)
#3. Assuming SPI boot, the sequence after H/W reset release is recognized as follows.
Correct?
After H / W reset release → PLL lock start → PLL lock complete → IC internal reset release → SPI access start (boot image load start)
>> If the minimum reset time is met and clock and all power supplies are stable then the bootloader will start firmware download after tRR time.
Rashi