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USB superspeed peripherals Forum Discussions

inal_2949331
Level 3
Level 3
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Hi,

I would like to control integrity of the data running over GPIF bus. There are some special registers GPIF_CRC_CONFIG and GPIF_CRC_DATA. Could you please explain how to use them?

Regards

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Hi

As of now we don't have any firmware example code to run CRC engine on GPIF

Thanks & Regards

Abhinav

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inal_2949331
Level 3
Level 3
5 likes given First like given Welcome!

Hi,

So, we have (from EZ-USB® FX3™ Technical Reference Manual) 3 registers to configure and run CRC engine:

1. GPIF_CRC_CONFIG (0xE0014124) - ENABLE, CRC_ERROR, BYTE_ENDIAN, BIT_ENDIAN bits, CRC_RECEIVED[15:0] - A CRC value received on the data inputs by the state machine. (Not sure understanding this right...)

2. GPIF_CRC_DATA CRC (0xE0014128)  - CRC_VALUE[15:0], INITIAL_VALUE[15:0]

3. GPIF_CRC_CONFIG (0xE0014130) - FUNCTION[15:0] - Contains the truth tables for user-defined transition functions. (Looks like here we define CRC polynomial?)


As a test I tried to set ENABLE bit, defined FUNCTION[15:0] = 0xA001, INITIAL_VALUE[15:0] = 0xFFFF. After all, I initiated a transfer over GPIF and expected to see any changes in CRC_VALUE[15:0]. But it remained zeroed as it was...

I believe many people are interested in reliability of devices based on FX3. Sure, FX3's USB subsystem deals with data integrity problems over cable, but what about GPIF bus? I would like to hear Cypress experts or any one, who solved this problem.

Best regards

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Hi

As I know this community thread is the only way to get technical support from Cypress. Is there any chance to get answer for my question?

Thanks a lot!

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Hi

As of now we don't have any firmware example code to run CRC engine on GPIF

Thanks & Regards

Abhinav

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