FX3 EZ-USB GPIO[17] (a.k.a. CTL[0]) state in USB boot mode wrong?

[SaGi_4116301]

Hi,

According to table 31 in AN76405 "EZ-USB® FX3™/FX3S™ Boot Options" the state of GPIO[17] a.k.a. CTL[0] is "Tristate" 

"while the bootloader is executing".

I have some questions related to that table.

Questions:

1) What is meant exactly by "while the bootloader is executing"? Does this table apply when you just plug the EZ-USB board into USB, before loading any firmware, so when the device enumerates as "Cypress FX3 USB Bootloader Device"?

2) The document  AN76405 states that the state of GPIO[17] a.k.a. CTL[0] is "Tristate". However, in the situation described under 1) I measure that GPIO[17] is HIGH (in my case 3.3V). Is this correct? My PMODE pins [2,1,0] are low,high,high (USB boot).

The question is relevant, because I use GPIO[17] as RESETN pin for an image sensor. When I first plug in the EZ-USB board into USB, I want GPIO[17] to be LOW to keep the image sensor in reset, before I load the actual firmware over USB. I tried a weak external pull down on GPIO[17] but that did not work, so it is definitely not in a TRISTATE condition as AN76405 suggests... 

[Rashi_Vatsa]

Hello,

Please find my comments below

1) What is meant exactly by "while the bootloader is executing"? Does this table apply when you just plug the EZ-USB board into USB, before loading any firmware, so when the device enumerates as "Cypress FX3 USB Bootloader Device"?

>> Yes, "while the bootloader is executing"  means before the application firmware is programmed to FX3 and the bootloader is running on FX3.

2) The document  AN76405 states that the state of GPIO[17] a.k.a. CTL[0] is "Tristate". However, in the situation described under 1) I measure that GPIO[17] is HIGH (in my case 3.3V). Is this correct? My PMODE pins [2,1,0] are low,high,high (USB boot)

>> For USB Boot, the PMODE[2:0] should be Z11. Also, let me know how did you measure voltage on GPIO? Please let me know the value resistor used to pull down the GPIO

[SaGi_4116301]

Thanks,

Regarding PMODE[2:0] : the only thing I do to enforce USB boot is to apply PMODE jumper J4 on the EZ-USB board. The resulting PMODE pins [2,1,0] are low,high,high  (0,3.3V 3.3V) is what I subsequently measure at these pins with a digital volt meter.  I can succesfully boot over USB. In fact I can get live camera images, all works. I just want to get a "neat" and "clean" boot behaviour on GPIO[17]. By the way I run the EZ-USB board with 3.3V GPIOs (with that dedicated jumper in place).

I tried 2 different pull down resistors on GPIO[17]:

47kohm and 10kOhm. Both were not low enough to get a "safe" logical zero on GPIO[17] during boot load.

[Rashi_Vatsa · Accepted solution]

Hello,

Please let me know the status of J5 jumper status of CTL0 pin is checked. The J5 jumper on CYUSB3KIT-003 is expected to be removed when SRAM interface is not enabled. 

This is because, if J5 jumper is not removed, CTL0 pin will be pulled up ( Please refer to Superspeed explorer kit schematics )

[SaGi_4116301]

Hi Rashi,

Indeed, I have jumper jumper J5 in place, because I use the SRAM.

So that explains why CTL0 is high when I first power the board.

So I will use CTL1 then as RESETN signal for the sensor.

Can you please confirm that CTL1 is low when jumpers J2,3,4,5 are all present when I first power up the board?
Does it require an external pull down resistor on the sensor board to guarantee that CTL1 is low at first power up?

Once you confirm, I will rework the sensor PCB design..

Sander

[Rashi_Vatsa]

Hello,

You can refer to SuperSpeed explorer kit schematics (attached) , CTL1 ( GPIO[18]) is not pulled up to 3.3V as done for CTL0 (when J5 is populated)

As per AN76405, the default state of FX3 GPIO[18] while the bootloader is executing before
application firmware download,  is Tristate (USB Boot). So, a pull down resistor (10k ohm) will be required to pull down CLT1.