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USB superspeed peripherals

Level 3
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Level 3

According to AN65974 (slave fifo interface) & AN87216 (master interface), I have burned your provided image - AutoMaster.img into one of FX3 , modified the source code and interface definition of slave fifo interface as below and burned that image into another FX3 board.

1. In cyfxslfifosync.h, change the DMA buf count to 16 and consumer_pport_socket to socket 1

2. In interface definition of slave fifo sync, revise the address bus to 2 and dma configuration as attachments.

Data can be sent or received from slave side but the number of data received by slave is incorrect. Refer to the attachment, data is transmitted by master (BULK OUT), a few more garbage data is received by slave (BULK IN) no matter how much data is transmitted by master, please kindly advise. Thanks.

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