FX3 Async SRAM boot

[TeMa_2997106]

I want to use asynchronous SRAM boot mode.

Is there any documentation that details this mode?

Thanks,

Tetsuo

[JayakrishnaT_76]

Hello Tetsuo-San,

We are sorry, but currently we do not have a documentation that details SRAM boot mode. We have forwarded your query to our product development team, who will evaluate your query.

Best Regards,

Jayakrishna

[JayakrishnaT_76]

Hello Tetsuo-San,

FX3 SRAM booting support only 16bit and PMODE pins should be [2:0]=[F,0,F]

Actually there is no difference between SRAM booting and ADMux booting with respect to protocol, the main difference is PMODE pins, address/data multiplex and electrical timings, other than that rest of all is the same. The steps one have to follow for booting from ADMux is listed in the attached word file. One has to follow the exact steps for the whole boot process.

The address of each PP register is actually documented in Table 28. Processor Port Register Map which is found in AN76405. The  link to the same is given below:

https://www.cypress.com/file/201991/download

The register address of PP_SOCK_MASK_L is 0x8A and PP_SOCK_MASK_H is 0x8B.

One of our customers tried to implement this procedure and shared that he was able to boot successfully using Async SRAM Boot mode.  This approach is not fully tested from our end as we do not have a test setup at the moment. Please try this at your end and let us know the results.

[TeMa_2997106]

Jayakrishna-san,

Thank you for your reply.

Your answer has the following sentence:
”The main difference is PMODE pins, address / data multiplex, ...”

My understanding is that Async SRAM boot mode has separate addresses and data line. Is it correct? If yes, what should I do with the address? I want to configure an 8-bit address. Can it configure?

Thanks,
Tetsuo

[JayakrishnaT_76]

Hello Tetsuo-San,

Yes, your understanding is correct. Async SRAM boot mode has separate address and data line. The interface should be same as Async SRAM state machine available in GPIF II designer. The interface timings can be found in FX3 datasheet from Page 31. The timings should be met correctly as per that given in the datasheet for reading or writing from a given address.

[TeMa_2997106]

Jayakrishna-san,

Is it possible to set the address width arbitrarily?
I want to realize a configuration like the attachment.

Thanks,
Tetsuo

[JayakrishnaT_76]

Hello,

Can you please elaborate your last response and your target application? As per the attachment, I can find 2 FX3 devices. Please let me know if both the devices need to implement Async SRAM Boot. 

As per the default Async SRAM state machine in GPIF II designer,  the address bus is of 8 bits (1 byte). The address bus will correspond to GPIO[22:29]. This should not be changed while using Async SRAM Boot. Also, the signals CS#, INT# and RESET# wont be operational while the device is booting as the default interface does not make use of these signals.

[TeMa_2997106]

There are two ways to use it in the next model. One is as Device (No.1) and the other is as Host (No.2). Memory is also connected to both bus and I want to boot FX3 from here.

When will your company complete testing Async SRAM mode? And when will the material be detailed? For now, I'm afraid to use this mode because it have little information.

Thanks,
Tetsuo

[JayakrishnaT_76 · Accepted solution]

Hello Tetsuo-San,

We are planning to remove this boot mode from the existing documentation as we do not have a setup to validate this mode. Please use SPI boot mode for your application.