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sj_1680686
Level 1
Level 1

In the TRM, 4.2 Clock Management, it says that the master clock of up to 500 MHz can be generated. But I couldn't find how to do it anywhere. It seems the clock is fixed at 403.2 or 384 MHz. Is it possible to change this clock value?

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YatheeshD_36
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hello,

Yes, the system clocking is fixed at 403.2 or 384 MHz for 19.2 MHz crystal, which is configured using the setSysClk400 parameter in the CyU3PSysClockConfig_t structure passed to the CyU3PDeviceInit call.

The GCTL_PLL_CFG register holds the information about the PLL configuration.

We do not recommend increasing the PLL clk output for 19.2 MHz. If you need higher frequency system clock, you can use the 26-MHz or 52-MHz input clock. Please refer to Section 2.3.1.9 CPU Operating Frequency from the FX3 TRM.

Thanks,

Yatheesh

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1 Reply
YatheeshD_36
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hello,

Yes, the system clocking is fixed at 403.2 or 384 MHz for 19.2 MHz crystal, which is configured using the setSysClk400 parameter in the CyU3PSysClockConfig_t structure passed to the CyU3PDeviceInit call.

The GCTL_PLL_CFG register holds the information about the PLL configuration.

We do not recommend increasing the PLL clk output for 19.2 MHz. If you need higher frequency system clock, you can use the 26-MHz or 52-MHz input clock. Please refer to Section 2.3.1.9 CPU Operating Frequency from the FX3 TRM.

Thanks,

Yatheesh