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USB superspeed peripherals Forum Discussions

desd_4393836
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Hello,

I have a very critical question,

I have an FPGA (ARTIX7 C7A100T FTG256) communicating with FX3 USB3.0 chip and from another site with a wireless chip ADC.

When I download SLAVEFIFOSYNC .img to FX3 chip, I can only get BULK OUT and get 997 error for BULK IN. I read application note for AN65974.zip where It mentioned try USBBULKSOURCESINK with powerstat function. Now I can see "BULK IN" and "BULK OUT" streaming both in control center and in streamer.

I want FIFO application to work under this power stat function. Please help me.

1) is this hardware problem or software?

2) How to fix this problem?

3) With this .img file I tried to upload bitstream to FPGA and get error that it is not possible. how to fix this?

P.S.  Linux installation is not possible for EZ USB. very vague explanation in readme file.

Thanks,

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1 Solution
desd_4393836
Level 2
Level 2
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Thanks for all help, the problem was with FPGA, not FX3. but I learned a lot. thanks again all.

View solution in original post

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9 Replies
KandlaguntaR_36
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Hello,

Please confirm what is the dma channel that is created between BULK IN endpoint (with associated socket) and GPIF II producer.

If the BULK IN endpoint does not have the data or timeout occur, the host will app will show 997 error.

Ensure that the data is available to UIB consumer socket of GPIF II producer and UIB consumer DMA Channel.

Have you done any modifications to default slavefifo application note firmware? If not, please mention.

Regards,

Sridhar

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Updates: I realized that Bulk in should be empty and that is why I get 997 timed out error. FIFOSYNC firmware needs communication with FPGA and apparently is only for a spartan 6 FPGA.

Another example I found in SDK folder is "bulksinkauto". In this example, I see both data in BULK IN and BULK OUT. I can stream too. I also check successfull loop.

there was an application in AN84868 - Configuring an FPGA Over USB Using Cypress EZ-USB® FX3™. to configure FPGA. I uploaded fifosynch image as firmware in this application successfully. it says FPGA slave serial detected. but when I try to upload bitstream generated from vivado by clicking on "configuring" bottom, I get the error: " can't send configuration data to FPGA".

Please help...

Does the problem involve FX3 chip or FPGA? what is U0, U1 and U3 power stat? can this be the issue?

P.S. Linux compiler has a problem. can't find arm c and cpp compiler location. step by step help would help here too.

Thanks,

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desd_4393836
Level 2
Level 2
First like received

Also I noticed that I can only send configuration of maximum size about 8KB .bin file after that the transmission will freeze. prove attached.

pastedImage_0.png

interestingly, when I use .img file of USBBulkSourceSink firmware I can transfer out and IN unlimited:

pastedImage_0.png

What is wrong with the chip?

Thanks,

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Hello,

In bulksourcesink, the data received over BULK OUT endpoint is being discarded. Hence, there will be always enough DMA buffer space to receive data.

In another case, please check whether the DMA consumer socket is consuming the data.

Please create a new thread for issues in Linux platform. It would be easy to handle.

Regards,

Sridhar

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Thanks for the reply.

How can I check if the DMA socket consume the data? Do you mean FPGA does not consume data? Sorry if my question is very simple, I am new in here.

Is it normal to see this behaviour?

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Update:

1. I didn't modify anything in AN84868 . Although, I have different GPIOs connecting to init_b, program_b and done ports on FPGA. but I changed the code based on those ports.

I put the scope on both ports init_b and program_B

So program_B goes low and after that FPGA respond with a pulse low in linit_b. but the DMA buffer won't get empty. it remains full. I checked done port and FPGA do not send done signal.

Thanks,

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desd_4393836
Level 2
Level 2
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   Update:

The buffer saturation (if this is the correct term )solved by changing CY_FX_EP_PRODUCER from 0x01 to 0x02 !! and I don't know why.

Still can't get DONE signal from FPGA though.

Thanks,

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I can see that we have used endpoint CY_FX_EP_PRODUCER 0x01 in the firmware.

Is the thread (https://community.cypress.com/message/208762?et=watches.email.thread#208762 ) continuation of the this thread?

Regards,

Sridhar

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desd_4393836
Level 2
Level 2
First like received

Thanks for all help, the problem was with FPGA, not FX3. but I learned a lot. thanks again all.

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