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After much frustration with a board I am attempting to debug over JTAG, I decided to try debugging the same firmware on a cyusb3kit-001. I discovered the kit loads firmware properly. The way I am able to reproduce this problem is with Segger's "J-Link Commander" and typing "connect" then selecting "ARM9".
On the CYUSB3KIT-001, I get a good result:
J-Link>connect
Please specify device / core. <Default>: ARM9
Type '?' for selection dialog
Device>?
Please specify target interface:
J) JTAG (Default)
TIF>j
Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
JTAGConf>
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>1000
Device "ARM9" selected.
Connecting to target via JTAG
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x07926069, IRLen: 04, ARM926EJ-S Core
CP15.0.0: 0x41069265: ARM, Architecure 5TEJ
CP15.0.1: 0x1D112112: ICache: 8kB (4*64*32), DCache: 8kB (4*64*32)
Cache type: Separate, Write-back, Format C (WT supported)
ARM9 identified.
J-Link>
On my board, I get the following failure message:
J-Link>connect
Please specify device / core. <Default>: ARM9
Type '?' for selection dialog
Device>?
Please specify target interface:
J) JTAG (Default)
TIF>j
Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
JTAGConf>
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>1000
Device "ARM9" selected.
Connecting to target via JTAG
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x07926069, IRLen: 04, ARM926EJ-S Core
Using DBGRQ to halt CPU
Resetting TRST in order to halt CPU
CP15.0.0: 0x00000000: Unknown implementer code, Architecure Unknown architecture
J-Link: ARM9, 0 core
****** Error: Unable to halt CPU core
J-Link>
The part number on my board is as follows:
CYUSB3014-BZX
One difference between the two baords is the CYUSB3KIT-001 has a 0.1" 2x10 jtag connector, and my board has the 0.05" 2x5 JTAG header. I am using the Segger adapter board 8.06.02 J-LINK 9-PIN CORTEX-M ADAPTER.
Are there any special settings to the BOOT pins that are required to enable JTAG? Is there any special processor wiring connections that might cause this behavior?
Best regards,
Kirk Wolff
Wolff Electronic Design
CY-PRO
Solved! Go to Solution.
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Hi Kirk Wolff,
Please compare the schematic diagram of CYUSB3KIT-001 kit with that of your schematic and ensure that all the pins related to JTAG are connected properly. Please check TRST pin as I suspect that it may not be connected properly.
http://www.cypress.com/documentation/development-kitsboards/ez-usb-fx3-development-kit-cyusb3kit-001
Kindly check and update.
Thanks & Regards
Abhinav
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Hi Kirk Wolff,
Please compare the schematic diagram of CYUSB3KIT-001 kit with that of your schematic and ensure that all the pins related to JTAG are connected properly. Please check TRST pin as I suspect that it may not be connected properly.
http://www.cypress.com/documentation/development-kitsboards/ez-usb-fx3-development-kit-cyusb3kit-001
Kindly check and update.
Thanks & Regards
Abhinav