During the FX3 GPIF test, a CYU3P_PIB_ERR_THR0_WR_OVERRUN error occurred, and I wonder how to solve it

[cho0130]

I did the GPIF interface test through "SlaveFifoSync" Example Code.

The DMA size of FX3 was set to 16384 and the count was set to 6.

The FPGA sent 16384 bytes 10 times at 150us intervals through the GPIF interface to FX3.

I sent GPIF data referring to the Figure4 Write Sequence of the AN65974 document.

And I received GPIF data using the application "bulkloop" provided when installing the FX3 SDK on my PC.

I think we should receive data 10 from the application. However, I only received data 6 times.

It was confirmed that FX3 caused an error of "CYU3P_PIB_ERR_THR0_WR_OVERRUN" during debugging.

There was no "CYU3P_PIB_ERR_THR0_WR_OVERRUN" error when sending data 6 times from FPGA to FX3, and there was always an error when sending more than 7 times. I think this error occurs because the DMA count is set to 6.

And this is my questions.

If I write GPIF data from FPGA to FX3 and read the data from application, buffer will be empty, but I don't know why the "CYU3P_PIB_ERR_THR0_WR_OVERRUN" error occurs. And I wonder what I should do to avoid the above error.

[AliAsgar]

Hi,

The CYU3P_PIB_ERR_THR0_WR_OVERRUN error occurs when all the DMA buffers are filled, and no more data can be written. This usually happens when the host application is slow in reading the data from FX3.

1. Why is bulkloop application used to test the application? Could you try using the streamer host application. Start Streamer application and then send the data from FPGA to FX3. Does the OVERRUN error still occur?

2. What modifications are done to the default firmware example code provided in the SDK?

Best Regards,
AliAsgar

[cho0130]

Hi,  Thank you for your answer.

1. As you said, we tested using the "streamer" application, and the error "CYU3P_PIB_ERR_THR0_WR_OVERRUN" still occurs.

Strangely, however, in the "bulkloop" example, data was always received only 6 times on 10 transmissions, but in the "streamer" example, all 10 times received data normally.

However, we found a new problem with data breaking during repeated tests.

I sent GPIF data 10 times and received all 10 times for the first time to check and see hope.

2. I modified a few things in the example program.
First, epcfg.burstLen from 1 to 16.
Second, dmaCfg.size from 1024 to 16384.
Third, dmaCfg.count from 2 to 6.

[AliAsgar]

Hi,

1. Was streamer application started before FPGA sent data to FX3?

2. Could you explain a bit more on the " we found a new problem with data breaking during repeated tests."

Best Regards,
AliAsgar

[cho0130]

Hi,

1. Yes, the application was executed before the FPGA sent the data to FX3. We confirmed that running application increases the fail count by the number of "Xfers to Queues" every "Timeout Per Xfer(ms)" time.

2. I sent GPIF data of five patterns from FPGA to FX3.
1) The value increased from 1.
2) The value increases from 2.
3) The value increases from 3.
4) The value increases from 4.
5) The value increases from 5.

The data I send once is char array 16384byte.
The values of pattern 1 to 5 were repeated and transmitted as many times as desired.
ex> When transmitting GPIF data 10 times,
1) -> 2) -> 3) -> 4) -> 5) -> 1) -> 2) -> 3) -> 4) -> 5)
When data was received from the "streamer" application, we checked whether the data of five patterns was received normally using the memcmp function.
During several tests, non-zero values were returned from the memcmp function, so it was judged that the data was broken.

[AliAsgar]

Hi,

OVERRUN error could also occur if the data transmission on the GPIF is not terminated properly.

1. Could you let me know if DMA watermark flag is used to end the termination?

2. If watermark flag is used, could you check the formula calculation?

3. Could you send us the data that was sent and data that is received? We want to know where exactly in the buffer is the data breaking.

Best Regards,
AliAsgar

[cho0130]

Hi,

1. I'm not sure exactly what the watermark flag is. To notify the end of the transmission, keep the PKTEND signal from HIGH to LOW 1 clock and then put it back in HIGH state.
In the example code, we set it as follows.
CyU3PGpifSocketConfigure (0,CY_U3P_PIB_SOCKET_0,6,CyFalse,1);
CyU3PGpifSocketConfigure (3,CY_U3P_PIB_SOCKET_3,6,CyFalse,1);
The watermark value is 6, and the flagOnData is false, so the watermark flag is not used?

2. Maybe we're not using the watermark flag.

3. When 16384byte is sent 100 times from FPGA to FX3 every 150us period, data errors occur in any order in the application.
There are two types of data breaking.
The first is when all 16384bytes are not received.
The second is when the length is normal but the data order is reversed.
We capture some of the data errors that occur and deliver them to the Excel file.
In the first sheet of Excel, I captured the data I sent.
The second sheet and the third sheet partially captured the case of an error.

[cho0130]

Hi,

Referring to the AN86947 document, we tested by raising the values of "Packets per Xper" and "Xper to Queue" to reduce overhead and increase data transmission rates. As a result, it was confirmed that the PC application received it normally as much as it was sent from FPGA. However, as I asked you before, the error "CYU3P_PIB_ERR_THR0_WR_OVERRUN" still occurs. Everything seems to be done normally, so I'm not sure if I can ignore the error message.

[AliAsgar · Accepted solution]

Hi,

WR_OVERRUN error could also occur when data is sent during the GPIF thread switching.
In this case data is lost, also giving WR_OVERRUN error.

Kindly use the DMA ready flags and DMA watermark flags, to transfer data to FX3 with flow control.

Best Regards,
AliAsgar

[cho0130]

Hi,

Your help really helped me a lot. Thank you for your answer.