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weiminwang
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Usually, actions in the active state will be performed in every clock cycle, and the transition conditions are checked on each clock edge. My question is, in one clock cycle, after the data transfer action (like IN_DATA or DR_DATA) is performed,
will the transition trigger like DMA_RDY_THn or DMA_WM_THn need some cycles' latency to be asserted?
 
In my practice, it seems there is 1 clock cycle latency for DMA_WM_THn trigger:
DMA_WM_TH.png

The image is part of my state machine, the data bus is 32 bits. When watermark is set to 1 4-bytes-word, the state machine works well. In this case, the GPIF can continuously transfer data to DMA with no data loss.

However, to make this work out, it means there is 1 clock cycle latency for DMA_RDY_THn trigger. This is to say, in the clock cycle where the available size of the active DMA buffer for thread n is 1 word after the IN_DATA action be performed, the DMA_WM_THn must be asserted in next clock. Only in this case, the active DMA buffer for thread n will be fully filled before the stste transition / thread switch.
 
While it seems there is no latency for DMA_RDY_THn trigger according to an example in section 7.11 of TRM doc:

DMA_RDY_TH.png

In READDATA state, if there is clock latency for DMA_RDY_TH0 to be asserted, the DMA buffer for thread0 will be overrun.
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Hello,

In your state machine, After Thread1 is filled, even when thread0 DMA is not ready, you are switching to the State0 which will result in a PIB Thread0 Overrun. So, I would recommend you to update the statemachine with DMA_RDY_TH0 and DMA_RDY_TH1 trigger when you are using IN_DATA in thread0 and thread1 respectively.

As I mentioned earlier, there is no latencies for DMA_RDY_THx triggers.

Regards,
Ajeeth

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Ajeethkumar_P
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50 likes received 500 replies posted 100 solutions authored

Hi,

DMA_WM_THn and DMA_RDY_THn are dedicated flags and have no latencies.

DMA_WM_THn trigger is true when the active DMA thread crosses the transferred data above the watermark.

DMA_RDY_THn trigger is true when the DMA is ready to send or receive data.

You can refer to AN65974 for more details.

Regards,
Ajeeth

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Hi, thanks for your answer. However, when I try the following state machine, it ends up with  WR_OVERRUN error. It should work if there is no latency for DMA_RDY_THn trigger. Could you explain me why?

ping-pong-with-dma-rdy.png

 

I found something in a previous post that might be related to this.  In this post, you said "GPIF hardware have two kinds of outputs. Betas outputs are driven out when the new state is loaded. Thread switching signal is beta which caused a delay of 1 cycle in your project. "

Could you explain more detail about this? Take the above state machine as an example, in the first clock cycle after the state transit from state0 to state1, does the IN_DATA action still write the data to the DMA buffer of thread0 since the thread switching signal has not yet taken effect?
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Hello,

In your state machine, After Thread1 is filled, even when thread0 DMA is not ready, you are switching to the State0 which will result in a PIB Thread0 Overrun. So, I would recommend you to update the statemachine with DMA_RDY_TH0 and DMA_RDY_TH1 trigger when you are using IN_DATA in thread0 and thread1 respectively.

As I mentioned earlier, there is no latencies for DMA_RDY_THx triggers.

Regards,
Ajeeth

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