Hi,
We are using the GPIF II peripheral to transfer data with a Spartan 7 FPGA in synchronous slave mode. Originally, we had the FPGA source PCLK. However, after performing a timing analysis we found that we cannot guarantee timing at 100 MHz when the FPGA is sourcing the clock and that it's easier to meet timing if the FX3 sources the clock. As a result, we modified our GPIF design and FPGA Logic such that the FX3 sources the clock. The interface type is still set to "Slave" in the GPIF II designer. I found that communication works at 50 MHz but we start to see timing issues with the control signals at higher frequencies.
I looked at the SRAM master example that is distributed with the FX3 SDK and found that it calls CyU3PPibDllConfigure to enable the DLL. KBA210733 implies that I need to enable the DLL but it's unclear to me if the DLL should be enabled in our design because the KBA states "Interface clock driven by FX3 (Synchronous Master mode)". However, our GPIF design has the interface clock driven by the FX3 but the interface type is set to slave. The FPGA logic is being used to select the address (thread) and we want it to remain this way, which means we cannot change the interface type to master. Please tell me if I need to enable the DLL and if so, which settings I should use.
Thanks,
Michael
