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Hi,
I am sending data to FX3 GPIF from FPGA in Async mode. Data bus width is 16 bit. I toggle the SLWR in 10MHz, push the data to socket 0, and I am able to read the data in USB PC side using a python script. When I change the speed to around 5MHz (means SLWR strobing not PCLK), I am not able to get any data out of USB. There is no changes in Flag A or B and slwr lines. But everything works as expected if the SLWR strobing happens at 10MHz.
I am using the SlaveFIFO2b example code in my FPGA. I was thinking that in Async mode, SLWR does not depend on speed of the clock. Please let me know what I am missing here.
Solved! Go to Solution.
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Hello,
The problem can be from the interface signals generated from the Master.
Can you please share the logical traces of the flags and control signals from the FPGA.
We have sample FPGA codes in AN65974: https://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-inte...
Thanks,
Yatheesh