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HaMu_4778661
Level 2
Level 2

Hi,

The goal is to test the data transfer between PC and FPGA, FX3 is used as an interface in between.

I have used the code that is provided by AN65974 with no changes.

In the loop back case if constant data is sent there comes no error, but while incremental data is sent there comes flips.

I have attached the snapshot for the reference.

Flips.jpg

Is the data capturing too fast before the next data occurs ?

Is there any way to clear this ?

Regards,

Haarika M

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1 Solution
Hemanth
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Hi Haarika,

It could be timing issues. If the timing mentioned in Fig 3 and 4 of the AN65974 is correctly met, there should not be any problem from FX3 side.

Regards,

Hemanth

Hemanth

View solution in original post

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8 Replies
Hemanth
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First like given First question asked 750 replies posted

Hi Haarika,

It could be timing issues. If the timing mentioned in Fig 3 and 4 of the AN65974 is correctly met, there should not be any problem from FX3 side.

Regards,

Hemanth

Hemanth
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Hi Hemanth,

Thanks for your reply. We are using arria 10GX development board and in FPGA we dont see any timing issues, Initially there was timing issues and data was highly corrupted and later we downgraded the pclk from 100 MHz to 80MHz. With this change the timing issues disappeared and the data corruption also reduced and now we see some bit flips happening which we shared the snapshot earlier.

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Hemanth
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Can you please share the timing diagram captured using hardware analyzer?

Regards,

Hemanth

Hemanth
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Hi Hemanth,

Thanks for the reply. I have shared the Signal Tap & Control Center snapshots.

SignalTap.pngControlCenter.png

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Hi

Can anyone help me  in bringing out this ?

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Hemanth
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Hi,

Control center log shows that one line (DQ0/ DQ31) is always showing 0.

From your first post - "I have used the code that is provided by AN65974 with no changes."

By default, GPIF bus width is configured for 16 bit. I see that FPGA is driving 32 bit data bus. Can you please clarify about this.

Regards,

Hemanth

Hemanth
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Hi Hemanth,

#define CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT (1)

By default the value is defined as 1, this is configured as 32 bit.

Regards,

Haarika M

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Hemanth
Moderator
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First like given First question asked 750 replies posted

Hi Haarika,

Yes. You are right. It is 32 bit.

Can you please probe DQ0 and DQ31 lines on oscilloscope? Please check if they are toggling when you perform loopback operation.

Regards,

Hemanth

Hemanth
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