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USB superspeed peripherals

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I'm working on a project that uses a GPIF II Interface (connected to an FPGA) and a USB peripheral. I'm using the slave FIFO example (slfifosync) which is already really well documented. The only big things we changed are the DMA Channels to be Auto instead of Manual, the size (4k bytes) of the DMA buffers, the number of DMA buffers (2 with U2P, 16 with P2U) and we added some commands in the main thread function and other places to handle control transfers (coming from USB). Everything is working fine here.

Now we are at a point where we want to add some headers/footers directly into the Cypress Chip (CyUSB3) to repackage our messages coming from USB. So we changed the U2P DMA channel to Manual to begin with and checked if the bypass of the Manual instead of Auto would work. We added the "prod" signal and the callback as it was already in the initial slave FIFO example. But now, it seems like some commands sent from USB are well received and well responded but some aren't. Since I have a P2U Auto and a U2P Manual in this example, I'm wondering if there's some problems that can occur or if I'm missing something with the interrupt priority with the main CPU thread and the GPIF II.

Thanks in advance,


1 Solution
Moderator 100 solutions authored 50 solutions authored 50 likes received

Hello Keven,

From the above description, i understand that your end application is as following:

1. FX3 will be idle (no data transfers going on)

2. Host PC will send a command over bulk endpoint

3. FX3 will receive the command, parse it and send some (hardcoded) data to the FPGA

Apart from this, there would be no ongoing data transfers going on between the host and the FPGA other than this. Please confirm.

If this is the case, please do the following:

1.) Modify the channels between U2P and P2U to make them between UIB to CPU (manual) and CPU to PIB (manual) - This will make the CPU intervention possible to decode the command from USB.

2.) The host can send a command to FX3 over the USB endpoint.

3.) The CPU will receive the incoming buffer (containing the command) and you can parse the buffer and send the hardcoded data (already present in the firmware) to the PIB block.



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