Cx 3 Image Sensor Reference Clock (MCLK)

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Augustine_Yeh
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Hi Cypress

MCLK is computed using the following equation , Can you tell us How to get and select of  HighByte (mClkCtl) and LowByte (mClkCtl) 


MCLK = ( PLL_CLK/mClkRefDiv ) / [ ( HighByte (mClkCtl) + 1 ) + ( LowByte (mClkCtl) + 1 ) ]

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Hello,

As mentioned in the CX3 TRM, the MCLKCTL divider specifies the HIGH time and LOW time counted by the divided down PLL_CLK.
The upper eight bits define the HIGH time count (1-255) and the lower eight bits define the LOW time count (1-255). 

So based on the requirement of high time and low time the counter can be set. If you need MCLK with same  high time and low time then the below value can be used.

=>(6+1)+(6+1)=14

Regards,
Rashi

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Rashi_Vatsa
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Hello,

Please refer to section 1.7.5 of CX3 TRM . This section explains the details.

After deciding the counter value based on MCLK frequency, this KBA  Analysis of CX3 Clocking Parameters – KBA226758 - Cypress Developer Community. can be referred for the changes required in MIPI structure to configure the MCLK.

Please let me know if you have any queries on it.

Regards,
Rashi
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Augustine_Yeh
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Hi Rashi

Thank for your reply , I know mClkCtl and mClkCtl (counter parameter) ,  But document don't guideline how to select the counter parament value . Thank !!

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Rashi_Vatsa
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Hello,

MCLK  is provided to the external sensor for  testing purposes. So, the value of MCLK needs to be decided based on the sensor.

As per the CX3 TRM, below is the formula to calculate MCLK.

 MCLK = ( PLL_CLK/mClkRefDiv ) / [ ( HighByte (mClkCtl) + 1 ) + ( LowByte (mClkCtl) + 1 ) ]

To decide the mClkCtl value, you need to decide the MCLK value to test the sensor.

mClkRefDiv can either be 2/4/8, so if MCLK value needed by sensor is for example 24 MHz we need to tune the parameters like mClkRefDiv and mClkCtl such that we get MCLK as 24 MHz.

PLL_CLK value can be known based on the CX3 MIPI Receiver Configuration. You can refer to section 1.7.2 of CX3 TRM.

PLL_CLK = REFCLK * [(PLL_FBD + 1) / (PLL_PRD + 1) ] / (2^ PLL_FRS)

Please let me know if this is clear

If not, please let share the CX3 MIPI Receiver settings and expected MCLK frequency so that I can help you with the counter value

Regards,
Rashi
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Augustine_Yeh
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Hi Rashi

for example in equation part of [ ( HighByte (mClkCtl) + 1 ) + ( LowByte (mClkCtl) + 1 ) ]
I can select the sum of any value to be equal to 7  for 24Mhz as below . 

==>(2+1)+(3+1)=7 ( example for 24Mhz in Document)

==>(3+1)+(2+1)=7

==>(1+1)+(4+1)=7

I can select the sum of any value to be equal to 14  for 12Mhz as below.

==>(5+1)+(7+1)=14 ( example for 12Mhz )

==>(3+1)+(9+1)=14

==>(6+1)+(6+1)=14

 

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Hello,

As mentioned in the CX3 TRM, the MCLKCTL divider specifies the HIGH time and LOW time counted by the divided down PLL_CLK.
The upper eight bits define the HIGH time count (1-255) and the lower eight bits define the LOW time count (1-255). 

So based on the requirement of high time and low time the counter can be set. If you need MCLK with same  high time and low time then the below value can be used.

=>(6+1)+(6+1)=14

Regards,
Rashi
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Augustine_Yeh
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Hi Rashi

Do you has MCLK  test  report for jitter issue , Thank !!

 

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Hello,

Please let me know the reason/purpose for which MCLK test report is required.

Regards,
Rashi
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Augustine_Yeh
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Hi Rashi

I want to evaluate jitter issue with customer whether it is possible to use MCLK to design the final production for save cost , Thank !!

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Hello,

As per CX3 data sheet and the following KBAs we recommend to use external clock as input to image sensor as CX3 provides a clock output signal “MCLK” only for testing the image sensor. This signal is not suitable to use in final product.

Analysis of CX3 Clocking Parameters – KBA226758 - Cypress Developer Community

CX3 Hardware: Frequently Asked Questions - KBA9129... - Cypress Developer Community 

Regards,
Rashi
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