Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

USB superspeed peripherals Forum Discussions

shkuc_292731
Level 3
Level 3

Can i configure the FX3 GPIF data bus width as 24bit on Slavefifo mode with FPGA ?

0 Likes
1 Solution
abhinavg_21
Moderator
Moderator
Moderator
50 likes received 25 likes received 10 likes received

Hi,

Yes you can configure GPIF as 24 bit in the AN 65974.

Follow the following simple steps:

  1. Open the GPIF project provided with the AN65974.
  2. Select 8 Bit in Data Bus width in the left pane menus (select 24 Bit if 24-bit bus width is required)
  3. Save it and build the project by clicking Build > Build Project to generate the cyfxgpif2config.h file

   4. Set CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT to '0' in the cyfxslfifosync.h file.

   5. Build the project. This step generates the image file for the 8-bit Slavefifo application (for 24-bit Slavefifo if 24 Bit is selected in step 3)

Note: When the data bus width is changed to 8-bit, the address lines are mapped to GPIO 8 (A1) and GPIO 9 (A0), unlike GPIO 28 (A1) and GPIO 29 (A0) in the case of both 16-bit and 32-bit bus widths. Similarly, with the 24-bit bus width, address lines are mapped with GPIO 41 (A1) and GPIO 42 (A0). Pin mapping for address lines may change based on the number of control lines, data bus width, and number of address lines selected. Ensure that the external processor drives the address lines that are mapped to the GPIF interface per the selected bus width, number of address lines, and number of control lines.

Thanks & Regards

Abhinav

View solution in original post

0 Likes
5 Replies
abhinavg_21
Moderator
Moderator
Moderator
50 likes received 25 likes received 10 likes received

Hi,

Yes you can configure GPIF as 24 bit in the AN 65974.

Follow the following simple steps:

  1. Open the GPIF project provided with the AN65974.
  2. Select 8 Bit in Data Bus width in the left pane menus (select 24 Bit if 24-bit bus width is required)
  3. Save it and build the project by clicking Build > Build Project to generate the cyfxgpif2config.h file

   4. Set CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT to '0' in the cyfxslfifosync.h file.

   5. Build the project. This step generates the image file for the 8-bit Slavefifo application (for 24-bit Slavefifo if 24 Bit is selected in step 3)

Note: When the data bus width is changed to 8-bit, the address lines are mapped to GPIO 8 (A1) and GPIO 9 (A0), unlike GPIO 28 (A1) and GPIO 29 (A0) in the case of both 16-bit and 32-bit bus widths. Similarly, with the 24-bit bus width, address lines are mapped with GPIO 41 (A1) and GPIO 42 (A0). Pin mapping for address lines may change based on the number of control lines, data bus width, and number of address lines selected. Ensure that the external processor drives the address lines that are mapped to the GPIF interface per the selected bus width, number of address lines, and number of control lines.

Thanks & Regards

Abhinav

0 Likes

Thanks Abhinav. I shall do a quick evaluation using development kit and get back to you with my results.

0 Likes
shkuc_292731
Level 3
Level 3

Hi,

Can you please share the watermark calculation for the 24bit Slave fifo mode ? I am unable to get any data from FPGA.

0 Likes
shkuc_292731
Level 3
Level 3

hi ,

I have used the watermark value as 6 & able to test 24bit slave fifo successfully.

But i am unable to access SPI flash when 24bit GPIF is used. Can you please help me regarding this ?

0 Likes

Hi,

Could you please check whether the GPIO[53], GPIO[54], GPIO[55] & GPIO[56] of FX3 are correctly mapped? Please check Table 7 on page 16 of FX3 datasheet for pin configuration.

Thanks & Regards

Abhinav

0 Likes