CYU3P_GPIF_OP_THRn_READY & CYU3P_GPIF_OP_DMA_READY difference ?

[WadeChen]

Dear Supporter,

I have a question, describe the situation,

In a UVC/UAC/AI project , There are create three thread in the firmware, one for video、one for audio and the other one for AI data. Those data are all transmitted from the FPGA.

In my case ,  I have already set Thread_0_DMA_Ready(for video)、Thread_1_DMA_Ready(for audio)、Thread_2_DMA_Ready(for AI data) in GPIF II tool. as below figure. And I have call CyU3PGpifOutputConfigure() API to set DMA default configure in firmware source code ,

The result of the program execution is that everything is normal, but when I write/read FPGA register , it will cause the state machine to misbehave, like HRef & VSync sensor signal not  follow state machine rule. Finally , I found out after testing many times.

Because the hardware video DMA always keep active high without change to low, so it affects the VSync and HRef signal. 

But when I set 

CyU3PGpifOutputConfigure(6, CYU3P_GPIF_OP_DMA_READY, CyTrue);

CyU3PGpifOutputConfigure(11, CYU3P_GPIF_OP_DMA_READY, CyTrue);

CyU3PGpifOutputConfigure(12,CYU3P_GPIF_OP_DMA_READY, CyTrue );

The hardware video DMA  become normal, even when reading and writing the FPGA register, it is executing normally.(still side effect, but video data transmitted ok )  

Can someone tell me what's going on? and what's the difference between the two(CYU3P_GPIF_OP_THRn_READY & CYU3P_GPIF_OP_DMA_READY )? 

Thanks everyone.

[JayakrishnaT_76 · Accepted solution]

Hello,

1. Why do you want to use the API CyU3PGpifOutputConfigure () to configure the flags in firmware as it can be done in the GPIF II designer itself. Do you have a specific reason as to which this approach is used?

2. How do you write or read FPGA register? Is it done over I2C? If not, then can you please let me know how this is done.

3. We are still not clear about the problem. Do you mean to say that the flag is always HIGH and FX3 keeps on sampling the data from the FPGA without the flag going low? If not, then please elaborate the issue seen.

4. CYU3P_GPIF_OP_THRn_READY will configure the pin as a flag dedicated to the thread 'n'. But, CYU3P_GPIF_OP_DMA_READY will configure the pin as a flag for the currently addressed thread.

[WadeChen]

Hello JayakrishnaT_76 :

Thank you very much for your reply.

1. Why do you want to use the API CyU3PGpifOutputConfigure () to configure the flags in firmware as it can be done in the GPIF II designer itself. Do you have a specific reason as to which this approach is used?

Ans: Because I am not the first author of the source code, I try to keep the original architecture and design. Although I know both approaches are the same.

2. How do you write or read FPGA register? Is it done over I2C? If not, then can you please let me know how this is done.

Ans: Yes, I am using the I2C interface to communicate with the FPGA , and using non-dma I2C. So I think it should not cause hardward dma not to pull low.

3. We are still not clear about the problem. Do you mean to say that the flag is always HIGH and FX3 keeps on sampling the data from the FPGA without the flag going low? If not, then please elaborate the issue seen.

Ans: The problem is strange that it happens when FPGA read/write (Question (2)), otherwise, it works fine. I'll describe it more clearly ,  when FPGA HRef signal low and VSync signal low, then video data will start to transmit to FX3 ,  and I have designed a 4K size video data counter through GPIFII , and auto dma is also defined in the firmware code , so it's "Hardware DMA" right ? i don't need to control it DMA full/empty status. But it was affected by my FPGA reading and writing process. That is, it no longer continues the state change of (Hardware DMA)High/Low. Why? I do not understand. This causes the video image of FX3 to no longer receive.

4. CYU3P_GPIF_OP_THRn_READY will configure the pin as a flag dedicated to the thread 'n'. But, CYU3P_GPIF_OP_DMA_READY will configure the pin as a flag for the currently addressed thread.

Ans: This is exactly what I understand, thanks for your reply.

Please help me, everyone!

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[JayakrishnaT_76]

Hello,

Can you please elaborate the following line in your previous response:
"I have designed a 4K size video data counter through GPIFII"?

Based on my understanding from the above statement, you are making use of a GPIF II counter to track whether the DMA buffers are full or not. Please correct me if my understanding on the statement is wrong. If my understanding is correct, then why do you need flags to check for the buffer status? 

If you are using flags for the data transfer, then please let me know when the data is transferred. Is it possible to probe the interface signals and share them for our reference? Is it possible to share he GPIF II project with us?

Can you please change the FPGA read/write registers to DMA mode and see if the problem is reproducible with this too?

For understanding the problem better, can you please try toggling GPIOs from the state machine at the relevant states? You can probe these GPIOs using a logic analyzer. By this, we can understand if the state machine is being switched or not when you read/write the FPGA registers. This can be used to understand if FX3 is actually reading the data or not.