CX3 using 24-bit bus issue

[LeoChen]

Hi,

I'm connecting a sensor to CX3, sensor ouput 2400x1536@36fps with YUV2, accroding to this, I have configured the CX3 MIPI receive paras as below:

As shown above, the CX3 MIPI configuration seems fine, but there is an error at Out Pixel Clock, and using these configuration, I can't get image from sensor either, and can't get HSYNC and VSYNC. Could you tell me where is wrong and how to get iamge correctly?

[Rashi_Vatsa]

Hello,

Please refer to Q13 of this KBA  CX3 Firmware: Frequently Asked Questions - KBA9129... - Infineon Developer Community

The maximum CSI clock for 4 MIPI lanes (considering 0 blanking period) can be 300MHz. If the horizontal blanking period is higher, a higher CSI clock might work (provided that video bandwidth is not greater than GPIF bandwidth)

As the horizontal blanking period is less in your configuration, we would suggest using CSI clock <=300 MHZ (for 4 lanes)

[LeoChen]

Hi Rashi_Vatsa,

On my understanding, the CSI clock could be high,  that is sensor output data with high bit rate, but I think CX3 will receive these data for CX3 have fifo and buffer, is this right?

And any  way, I have tried to decrease CSI clcok to 300M, but the tool still output error as below:

[Rashi_Vatsa]

Hello,

On my understanding, the CSI clock could be high,  that is sensor output data with high bit rate, but I think CX3 will receive these data for CX3 has FIFO and buffer, is this right?

>> Yes, CX3 has FIFO

Please try the attached configuration and please ignore the errors

[LeoChen]

Hi Rashi,

On my understanding, the CSI clock could be high,  that is sensor output data with high bit rate, but I think CX3 will receive these data for CX3 has FIFO and buffer, is this right?

>> Yes, CX3 has FIFO

-> As CX3 has FIFO, then the sensor could output data more than 600Mbps/lane(sensor has 4 lane), CX3 can still get correct data, so why limit 600Mbps/lane when there is 4 lane for sensor?

[Rashi_Vatsa]

Hello,

As CX3 has FIFO, then the sensor could output data more than 600Mbps/lane(sensor has 4 lane), CX3 can still get correct data, so why limit 600Mbps/lane when there is 4 lane for the sensor?

>> The limitation is due to GPIF bandwidth i.e. 2.4Gbps. Also, the CX3 MIPI CSI-2 receiver block reads the data from the image sensor, de-serializes it, merges lanes,
de-packetizes it, and then sends it as a parallel input to the fixed-function GPIF II block

If the blanking period is more that would help to get more time to empty the FIFO 

[LeoChen]

Hi Rashi,

From your info, as GPIF just transfer active bit data, I think that as long as the total MIPI receive active bit rate is less than 2.4Gbps (H_active*V_active*fps*bit_per_pixel < 2.4Gbps), no matter the speed of each MIPI lane is (of course < 1Gbps/lane), CX3 will get MIPI data correctly. And get back to my configuration above, the MIPI bit rate is high, but total active bit rate < 2.4Gbps, so CX3 could receive data correctly  in theory. Is this right?

[Rashi_Vatsa]

Hello,

Yes, your understanding is correct. The 2.4Gbps limitation is from the fixed-function GPIF interface of CX3

[LeoChen]

Hi Rashi,

I have update sensor MIPI clock to 300MHz, and get below 2 different configuration, one is worked, one is not worked, could  you help to clarify the difference?

1) not worked configuration, and a error occured when print log

2) worked configuration, just decrease PCLK to 96MHz

[Rashi_Vatsa · Accepted solution]

Hello,

The video bandwidth is 2400*1536*16*36 = ~1.9Gbps and the max GPIF bandwidth is 1.6 Gbps when the GPIF bus width is 16 bits. To stream ~1.9Gbps, please configure the output bus width as 24 bits so that the maximum bandwidth of the GPIF interface can be used

Please note that zero padding will be done when the above change is done. The host application will have to discard the padded zeroes.