CX3 design review and MIPI layout question

[Sag]

Hey,

we designed a small board with CX3.
I'll be happy to get a review on the schematics and layout, especially on the USB super speed lines and the MIPI data 0 lines which are not layout great but we can't find a better alternative.

appreciate the help.

thanks, 

[AliAsgar]

Hi,

You can refer to the MIPI layout guidelines in the given application note:
https://www.infineon.com/dgdl/Infineon-AN90369_How_to_Interface_a_MIPI_CSI-2_Image_Sensor_With_EZ-US....

The CX3 schematic and layouts can be reviewed in section 14 of the given application note:

https://www.infineon.com/dgdl/Infineon-AN70707_EZ-USB_FX3_FX3S_SX3_hardware_design_guidelines_and_sc...

Best Regards,
AliAsgar

[Sag]

Hey AliAsgar,

we followed those guidelines, the issue is that given the very small size board and the location of the MIPI data0 balls it is very hard to layout the traces, please see the picture below. since the trace is short, will this work?

thanks, 

[AliAsgar · Accepted solution]

Hi,

I have reviewed the schematics and the layout. The schematics seem fine, but i have some comments for the layout.

1. The trace spacing between the MIPI data lanes must be twice the trace width. I found that the trace width was almost equal to the trace spacing between the MIPI lanes.

2. It is not advised to keep any via on the SSUSB traces. I found that there was a via on the SSTX lines.

Please review these changes.

Also make sure that the impedance on the MIPI data lanes are approx 100ohms.

Best Regards,
AliAsgar

[Sag]

hey,

the MIPI data lanes were corrected to 100ohm differential, and indeed the trace gap increased.

regarding the SSUSB lines, i know about the VIAs, however due to the very small board there is actually not other way...

thanks for the comments.

[AliAsgar]

Hi,

Do you have any other queries?

Best Regards,
AliAsgar

[Sag]

not at the moment.

thanks for the help.