CX3-Fifo Delay Time

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LeoChen
Level 3
Level 3
25 replies posted 50 sign-ins 10 replies posted

Hi,

How to calculate FIFO Delay Time as CX3 MIPI Interface Confiduration show. Could you give me any formula to calculate this value? Thanks!

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1 Solution

Hello,

Please find the formula below:

Fifo Delay time = ((Fifo Delay * 4/Number of Lanes) + 10)/(CSI_Clock/4)

Best Regards,
Jayakrishna

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8 Replies
JayakrishnaT_76
Moderator
Moderator
Moderator
First question asked 1000 replies posted 750 replies posted

Hello,

Can you please let me know why this information is needed? The tool actually calculates the value of this parameter internally and shows if the value is proper or not.

Best Regards,
Jayakrishna
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Hi  

I have sevral sensors connect to CX3 with one firmware, sensor setting will be sent to CX3 by UVC XU, and I want to calculate CX3 MIPI interface configuration by firmware, so I want to know how to calculate thses params. Thanks!

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Hello @LeoChen,

Thank you for the information. As per my understanding, "UVC XU" means extension unit. Please correct me if my understanding is wrong.

I am checking internally on the calculation of this parameter. I will update the thread as soon as I have an update.

Best Regards,
Jayakrishna
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JayakrishnaT_76
Moderator
Moderator
Moderator
First question asked 1000 replies posted 750 replies posted

Hello,

Please find the details on Fifo delay and its calculation below:

FIFO delay:

It is necessary that the output data rate should be greater than or equal to the input data rate to prevent data loss.

When you are keeping the Pixel clock same as minimum suggested by the tool the output and input data rate will be equal. There is a chance that the output parallel pixel clock is set higher than the minimum value suggested by the tool. In this case fifo delay is necessary.

JayakrishnaT_76_2-1648027679206.png

 

Fifo delay adds delay to the parallel output at the beginning of each line. Minimum value of the fifo delay is calculated as follows:

Hactive (MIPI CSI-2)- Hactive (parallel).

The maximum value of the fifo delay time will account the internal line buffer as well. The tool will automatically take care of this calculation.

You can set the fifo delay time to the minimum value required.

FIFO delay parameter should be carefully chosen such a way that the current MIPI Line data should be sent out completely over the parallel interface before the next MIPI line data arrives. If this rule is violated, vertical splits can be observed in the video frame.

Best Regards,
Jayakrishna
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Hi JayakrishnaT_76,

Thanks for your support.

I have another question accroding to your above answer, how could fifo delay value match with fifo delay time? Is there still a formula to transfer fifo delay value to fifo delay time?

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Hello,

Sorry for the confusion created. By minimum value of fifo delay, I actually meant minimum value of fifo delay time. The minimum fifo delay time can be calculated as follows:

Min Fifo delay time = Hactive (MIPI CSI-2)- Hactive (parallel)

Best Regards,
Jayakrishna
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Hi JayakrishnaT_76,

I know your description, but still confused how Fifo delay xx byte -> Fifo Delay time as below picture show.

 

 

 

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Hello,

Please find the formula below:

Fifo Delay time = ((Fifo Delay * 4/Number of Lanes) + 10)/(CSI_Clock/4)

Best Regards,
Jayakrishna
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