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USB superspeed peripherals Forum Discussions

Milka
Level 2
Level 2
10 replies posted 10 sign-ins 5 replies posted

Hi all!!,

i'm using boardkit FPGA and FX3 and i have problem with streaming data to PC.
i send test data with fixed size samples (16 points to PC) from FPGA to PC. And i think... FX3 works wrong.

sometimes i save ok raw data but sometimes data is broken and at low speeds and high the same result (periodically data is broken)

I try to divide frequency on FPGA to send data on FX3 but it's doesn't solve my problem.
At this time i doens't known what i do to fix this problem.

FX3 sources include:

Slave FIFO Synchronous mode
32 bit regime to transfer data from FPGA to PC
create two BULK IN, BULK OUT endpoints

FX3 EZ USB Suite Project, attachement to message! Thanks ALL!

 

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1 Solution
Rashi_Vatsa
Moderator
Moderator
Moderator
5 likes given 500 solutions authored 1000 replies posted

Hello,

Please find my comments

I am attaching a screenshot of the USB Control Center - it's strange that the maximum packet size shows 2048, in linux ( cyusb_linux - show 1024)

>> From the firmware, the endpoint burst length (BURST_U2P_LEN/BURST_P2U_LEN) is set to 2 so the maximum packet size is 2048 (2*1024). You can set the burst length to 16 is you want endpoint size as 16KB

After downloading more than 100 MB of data, they arrive incorrect.

>> The watermark value is set 8 which means that for writing data to FX3 the data should be written for 4 clock cycles after watermark flag is asserted.

 The number of data words that may be written after the clock edge at which the partial flag is sampled low is 4 ( 8*1 - 4 = 4). Please confirm if this is handled in the fpga code and the write sequence timing mentioned in section 5.2 of AN65974 is met.

The DMA ready flag should be monitored for starting the DMA transfer and the DMA watermark should be monitored for stopping the data

>> Please share the snippet (control center/streamer) of the data received when mismatch is seen. 

Also share the interface signals (DMA flags, PCLK, SLWR, SLCS, data) when the problem is seen for us to check

Regards,
Rashi

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5 Replies
Rashi_Vatsa
Moderator
Moderator
Moderator
5 likes given 500 solutions authored 1000 replies posted

Hello,

To understand the problem better I have few questions based on your description

I send test data with fixed size samples (16 points to PC) from FPGA to PC. And i think... FX3 works wrong.

- Please confirm if you meant that 16 bytes of test data is being sent from FPGA to FX3 (and then to USB host)

sometimes i save ok raw data but sometimes data is broken and at low speeds and high the same result (periodically data is broken)

>> Please elaborate this. Is the test data received on USB host ? 

Please let me know if the FPGA code files attached with AN65974 is used on the FPGA side or is it the custom FPGA code.

Also, please confirm if some changes are done to the GPIF state machine. If yes, please share the .cyfx file.

In the firmware the CyU3PDebugPrint calls are commented out. Please let me know if the UART port is accessible on the board and can you capture UART debug  prints

 

Regards,
Rashi
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Milka
Level 2
Level 2
10 replies posted 10 sign-ins 5 replies posted

Hi Rashi!

- Please confirm if you meant that 16 bytes of test data is being sent from FPGA to FX3 (and then to USB host),

No! I send 32 bit data from FPGA to FX3, i make data from 2x16 bit channels and configure slave fifo to 32 bit.

I used default project from cypress site, but i change 16 bit to 32 bit bandwidth:

https://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-inte...

>> Please elaborate this. Is the test data received on USB host ? 

Yes! Data complete transfered from PC program to USB host and i change variables frequency, number of points.

>>> Please let me know if the FPGA code files attached with AN65974 is used on the FPGA side or is it the custom FPGA code.

>>>Also, please confirm if some changes are done to the GPIF state machine. If yes, please share the .cyfx file.

YES I using default SlaveFifo .cyfx project & i change 16 bit to 32 bit bandwidth.

>>>In the firmware the CyU3PDebugPrint calls are commented out. Please let me know if the UART port is accessible on the board and can you capture UART debug  prints

I'm not using UART data with FX3, but i can restore default state of uart debugging. 

 

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Rashi_Vatsa
Moderator
Moderator
Moderator
5 likes given 500 solutions authored 1000 replies posted

Hello,

Please find the attached firmware with some added debug prints. 

Please initialize the UART debugging (CyFxSlFifoApplnDebugInit) and enable all the  CyU3PDebugPrint calls and share the UART debug prints

In the thread description you mentioned that "And i think... FX3 works wrong." Please let me know why do you say that as the data is received on the PC/USB host correctly. I understand that the data is being sent from FPGA>PIB>USB Host (PC). Is this correct?

I understand that the GPIF bus width is changed to 32 bits. Let me know how much total data is sent from FPGA to FX3

Regards,
Rashi
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Hi Rashi! Thank you for you replyes. Sorry for the long answer.

At now i see in my project alternative streamIN - SlaveFifo2b VHDL code and i attach this vhdl to this message.

My project based on this example: https://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-inte...
But 1 little change - I change size of GPIF II to 32 bit - this №86 line in cyfxgpif2config.h

I understand that the data is being sent from FPGA>PIB>USB Host (PC). Is this correct?

No - fpga and fx3 are on the same board. I am attaching a .xdc file to show where the signals are coming from

And I Attach top module of my project. To show you how i generate messages and send to FX3 FIFO. And EZ USB Project.

Message consist of 2 - 16 bit vectors. 1 - vector - counter (0xFF,5,..16), when 0xFF - Label of start; 5 - constant, 2,3,4...16 - data of counter. 2 vector - other data.

At now i read to PC - 1 vector with counter and check data.
After downloading more than 100 MB of data, they arrive incorrect.

Maybe i incorrect generate messages to FIFO and check flags.

I am attaching a screenshot of the USB Control Center - it's strange that the maximum packet size shows 2048, in linux ( cyusb_linux - show 1024)

At now i go to initialize uart...

Thank you!

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Rashi_Vatsa
Moderator
Moderator
Moderator
5 likes given 500 solutions authored 1000 replies posted

Hello,

Please find my comments

I am attaching a screenshot of the USB Control Center - it's strange that the maximum packet size shows 2048, in linux ( cyusb_linux - show 1024)

>> From the firmware, the endpoint burst length (BURST_U2P_LEN/BURST_P2U_LEN) is set to 2 so the maximum packet size is 2048 (2*1024). You can set the burst length to 16 is you want endpoint size as 16KB

After downloading more than 100 MB of data, they arrive incorrect.

>> The watermark value is set 8 which means that for writing data to FX3 the data should be written for 4 clock cycles after watermark flag is asserted.

 The number of data words that may be written after the clock edge at which the partial flag is sampled low is 4 ( 8*1 - 4 = 4). Please confirm if this is handled in the fpga code and the write sequence timing mentioned in section 5.2 of AN65974 is met.

The DMA ready flag should be monitored for starting the DMA transfer and the DMA watermark should be monitored for stopping the data

>> Please share the snippet (control center/streamer) of the data received when mismatch is seen. 

Also share the interface signals (DMA flags, PCLK, SLWR, SLCS, data) when the problem is seen for us to check

Regards,
Rashi