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USB superspeed peripherals Forum Discussions

StSa_4592716
Level 1
Level 1

I have a project where I need to read in 12 SPI ADCs simultaneously using a common MOSI, SCLK, and CS. Therefor I need to bit-bang the SPI. I was looking at cyfxusbspiregmode as an example, but when I run it on the EZ-USB FX3, it seems very slow, with about a 6usec clock cycle. There are two 1usec delays, which, when removed, gets it down to 4usec. Adding the define to use direct register mode, gets it down to 3 usecs. This still seems really slow, given a processor clock of 200MHz. I'm just getting started with this device, so maybe I'm missing something basic. I've bit-banged SPI on the Teensy with speeds in the MHz.

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Hi,

The result that you are getting would be the maximum that can be achieved.

The PCLK for FX3 is 200MHz but it goes through a series of internal clock dividers which introduces the delays.


Regards,

Yashwant

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YashwantK_46
Moderator
Moderator
Moderator
100 solutions authored 50 solutions authored 50 likes received

Hello,

Please refer to the attached link for KBA : Increasing Frequency of Bit-Banged GPIO Clock in EZ-USB® FX3™ - KBA90267

Please use cyfxusbspigpiomode found in the SDK example path: C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\serialif_examples\cyfxusbspigpiomode

Please use the above mentioned firmware and make the necessary changes to you application and see if it suits your needs.


Regards,

Yashwant

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Thanks for the link! I missed that in my search.

I changed the CyU3PGpioSetValue to CyU3PGpioSimpleSetValue and also used that to set the clock high and low (it was calling a routine for that). That brought it down to a bit under 2usec.

I also realized when I used the alternate method in the code  (*regPtrMOSI |=    CYFX_GPIO_HIGH;) I had failed to remove the 1usec delays. That method now is about 1usec clock period.

I'm assuming that's about as good as it will get? I was hoping for a 10x improvement.

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Hi,

The result that you are getting would be the maximum that can be achieved.

The PCLK for FX3 is 200MHz but it goes through a series of internal clock dividers which introduces the delays.


Regards,

Yashwant

Thanks, I'll try another approach then.

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