Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

USB superspeed peripherals Forum Discussions

MehtaExpai
Level 1
5 replies posted 5 sign-ins First reply posted
Level 1

Infinion.png

While performing loopback test using Cyclone 10 gx development kit and cypress fx3 (Super speed Explorer Kit) facing error during bulk in transfer (error code :- 997) 

0 Likes
1 Solution
AliAsgar
Moderator
Moderator 750 replies posted 50 likes received 500 replies posted
Moderator

Hi,

BULK OUT transfers are failing after DMA_BUFFER_COUNT number of transfers, as the already committed DMA buffers are not consumed by the FPGA, hence resulting in failures.

As FPGA has not received data properly, it is not able to send anything back. Hence all the BULK IN transfers are failing.

I assume default SlaveFifoSync firmware is being used in your application.
If thats the case, please check the connection between FX3 and FPGA and make sure the FPGA is working as programmed.

When FX3 has to send data to FPGA, we expect a SLRD to be asserted by the FPGA, based on the flags asserted as per the DMA status. 

Could add counters to the DMA callbacks and check if there are any PROD or CONS event occurring?

Best Regards,
AliAsgar

View solution in original post

0 Likes
11 Replies
JayakrishnaT_76
Moderator
Moderator First question asked 1000 replies posted 750 replies posted
Moderator

Hello,

As you might be knowing, error code: 997 refers to a timeout error. This can occur if the DMA buffer associated with the DMA socket corresponding to EP1 IN (i.e 0x81) is empty. Could you please confirm that the FPGA has received the data that was sent to the endpoint 0x01 from the USB host. If yes, then please also confirm that the data is looped back properly to FX3's GPIF II interface by the FPGA.

Best Regards,
Jayakrishna
0 Likes
MehtaExpai
Level 1
5 replies posted 5 sign-ins First reply posted
Level 1

Hello,

As you suggested I have checked the signals (FLAGS),   i have checked all flags(FLAG A, FLAG B, FLAG C and FLAG D) using signal tap logic analyzer and  getting all of the flags high when my fx3 is programmed and connected to FPGA as i disconnect my FX3 from FPGA all flags are low. But when i send any data using bulk out no any changes found in flags.

0 Likes
AliAsgar
Moderator
Moderator 750 replies posted 50 likes received 500 replies posted
Moderator

Hi,

Is the BULK IN transfer always failing?

I assume you have two DMA channels, one is from USB To GPIF (UToP) and another is one from GPIF to USB (PToU). Please register callbacks for these and enable notifications for PROD and CONS events.

Print the occurrence of the UtoP PROD, UtoP CONS, PtoU PROD and PtoU CONS events from the DMA callback using the UART debug prints. Note that blocking calls like Print should not be called in the Callback functions. It can be called in the for (;;) loop.

Best Regards,
AliAsgar

0 Likes
MehtaExpai
Level 1
5 replies posted 5 sign-ins First reply posted
Level 1

Hi, 

Yes, Bulk In transfer is always failing.

Yes, Having two DMA channels. This all things mention by you are already there.

0 Likes
AliAsgar
Moderator
Moderator 750 replies posted 50 likes received 500 replies posted
Moderator

Hi,

I would want you to increment counters for each of these events and print in the for loop and share the UART debug prints with me.

Also please perform a BULK OUT transfer, BULK IN transfer and share with us the waveforms of the interface signals during the whole process.

Is the BULK OUT working always, or does it fail after few transfers? If yes, after how many transfers?

Best Regards,
AliAsgar

 

0 Likes
MehtaExpai
Level 1
5 replies posted 5 sign-ins First reply posted
Level 1

Hi,

As per your suggestion i have attached photos of waveform and code. 

Yes , BULK OUT transfer fails after 2 or 3 transfers and Bulk in transfer fails every time.

I didn't find any impact on waveform after bulk out transfer and bulk in transfer. (Whenever FX3 programmed and connected with FPGA  all flags will be high, but not getting any changes during bulk out transfer)

 

Infinion.png

FX3_FPGA connected.png    FX3_FPGA connected.pngfx3_fpga_not connected.pngInfin.png

0 Likes
AliAsgar
Moderator
Moderator 750 replies posted 50 likes received 500 replies posted
Moderator

Hi,

It seems that FPGA is not communicating properly with FX3. There is no assertion of SLRD or SLWR during the process. 
"Whenever FX3 programmed and connected with FPGA  all flags will be high, but not getting any changes during bulk out transfer" 

>> But in the last photo I see that the flags are low, could you let me know when do flag become high to low?

Could you let us know what code is programmed on the FPGA?

Best Regards,
AliAsgar

 

0 Likes
MehtaExpai
Level 1
5 replies posted 5 sign-ins First reply posted
Level 1

Hi,

Whenever my FX3 was not programmed all flags set to low. As i programmed my FX3 and connect it to FPGA, FLAGs becomes high (But for not every time). Some times flags didn't become high even after i connect my programmed FX3 to FPGA.  Here i have attached my top level file and sdc file for your reference.

 

0 Likes
AliAsgar
Moderator
Moderator 750 replies posted 50 likes received 500 replies posted
Moderator

Hi,

BULK OUT transfers are failing after DMA_BUFFER_COUNT number of transfers, as the already committed DMA buffers are not consumed by the FPGA, hence resulting in failures.

As FPGA has not received data properly, it is not able to send anything back. Hence all the BULK IN transfers are failing.

I assume default SlaveFifoSync firmware is being used in your application.
If thats the case, please check the connection between FX3 and FPGA and make sure the FPGA is working as programmed.

When FX3 has to send data to FPGA, we expect a SLRD to be asserted by the FPGA, based on the flags asserted as per the DMA status. 

Could add counters to the DMA callbacks and check if there are any PROD or CONS event occurring?

Best Regards,
AliAsgar

0 Likes
MehtaExpai
Level 1
5 replies posted 5 sign-ins First reply posted
Level 1

Hi,

I am using default SlaveFifoSync firmware to programme FX3 and Slavefifo2b_loopback to programme FPGA. In slavefifo2b_loopback  clk_100 used in each always statement but clk_100 was not mentioned as input or output anywhere so could you please help me regarding these. 

 

0 Likes
AliAsgar
Moderator
Moderator 750 replies posted 50 likes received 500 replies posted
Moderator

Hi,

Please refer to the slaveFIFO2b_loopback.sdc files to check the declaration of clk_100.

Please check if the FPGA is working fine and let me know if you still face the error.

Best Regards,
AliAsgar

0 Likes