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USB superspeed peripherals

JaYe_3798301
Level 2
Level 2

Hi,

I am developing a product with Fx3s. And would like to use the GPIF II interface to interact with an FPGA.

As the first step, I used two Fx3s and one acted as the master and the other as the slave.

My question is: how to compute the number of clocks needed to read from and write to the slave side?

The following experiment were done with the default source code of AN87216 with the only change to modify the data bus width from 32 to 16.

1. Fx3 master read from fx3 slave (8bytes sent from slave out endpoint in control center)

RD_ signal last for 8 clock cycles (I think it should be 4 if bus bit width is 16 ???)

read.png

2. Fx3 master write to fx3 slave (8bytes sent from master out endpoint in control center)

WR_ signal last for 6 clock cycles (I think it should be 4 if bus bit width is 16 ???)

write.png

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1 Solution
YashwantK_46
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Moderator

Hi,

Regarding the 1st timing diagram:

->Data sampling starts as soon as CS (trigger point) gets asserted and is done for the next 4 clock cycles ( 8-bit data ).

->In the 5th clock cycle, the state machine transitions to the next state and asserts FLAGA and FLAGC.

-> Due to some internal latency, FLAGA and FLAGC get asserted some nanoseconds after the 5th clock and so, they are sampled in the 6th clock.( You can verify by zooming into the trace and having markers to measure the exact point at which FLAGA get asserted)

->Because SLRD is early, it gets de-asserted in the 8th clock cycle( 2 cycles after FLAGA and FLAGC).

->Since it is a short packet, there is an additional 1 cycle delay in INTR_CPU and commiting the packets to the host.

That's the reason why you have 8 clock cycles for the operation instead of 4 clock cycles.

Regards,

Yashwant

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5 Replies
YashwantK_46
Moderator
Moderator 100 solutions authored 50 solutions authored 50 likes received
Moderator

Hi,

I am trying to reproduce the scenario on my end.

Can you please confirm the changes that you did to the GPIF State Machine of both the master and the slave?

I have seen that you mentioned that you are trasnferring 8 bytes. Can you please confirm this?


Also, did you change the bus width to 16-bit in both the state machines?

Regards,
Yashwant

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JaYe_3798301
Level 2
Level 2

Hi,

The only changes I did in both GPIF and firmware were to change the data bus from 32 to 16.

Yes. I sent 8 bytes data from the control center.

By the way, the reading and writing result were correct.

The Fx3 master did write and read correct amount of data and correct values to and from the slave.

I am just wondering the clock cycles needed in the read and write are different and are not equals to 4 as I assumed.

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YashwantK_46
Moderator
Moderator 100 solutions authored 50 solutions authored 50 likes received
Moderator

Hi,

Regarding the 2nd timing figure:

->Data sampling starts as soon as CS (trigger point) gets asserted and is done for the next 4 clock cycles ( 8-bit data ).

->In the 5th clock cycle, the state machine transitions to the next state and asserts PKTEND and SLWR also.

->But, since SLWR is a delayed, it will get de-asserted in the next clock cycle.

And that's why you see 6 clock cycles instead of 4.

I will get beck to you soon regarding the 1st timing diagram.


Regards,

Yashwant

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JaYe_3798301
Level 2
Level 2

Hi,

Thanks a lot for your reply on the Fx3 master write to Fx3 slave situation.

Need help on the Fx3 master read from fx3 slave(1st timing diagram) as well.

Thanks in advance.

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YashwantK_46
Moderator
Moderator 100 solutions authored 50 solutions authored 50 likes received
Moderator

Hi,

Regarding the 1st timing diagram:

->Data sampling starts as soon as CS (trigger point) gets asserted and is done for the next 4 clock cycles ( 8-bit data ).

->In the 5th clock cycle, the state machine transitions to the next state and asserts FLAGA and FLAGC.

-> Due to some internal latency, FLAGA and FLAGC get asserted some nanoseconds after the 5th clock and so, they are sampled in the 6th clock.( You can verify by zooming into the trace and having markers to measure the exact point at which FLAGA get asserted)

->Because SLRD is early, it gets de-asserted in the 8th clock cycle( 2 cycles after FLAGA and FLAGC).

->Since it is a short packet, there is an additional 1 cycle delay in INTR_CPU and commiting the packets to the host.

That's the reason why you have 8 clock cycles for the operation instead of 4 clock cycles.

Regards,

Yashwant

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