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WGT_4383351
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Why is it :

RD_WR_IDLE--(if FLAGA)-->DR_ADDR--(if FLAGA & &DMA_RDY_TH0)-->RD_CTRL

can this work too:

RD_WR_IDLE--(if FLAGA & &DMA_RDY_TH0)-->DR_ADDR--(if true)-->RD_CTRL

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Hello,

As shown in the slave read sequence,

pastedImage_0.png

The flow in the GPIF II designer:

                                   RD_WR_IDLE--(if FLAGA)-->DR_ADDR--(if FLAGA & &DMA_RDY_TH0)-->RD_CTRL

As soon as FLAGA is asserted, the address line A0 is asserted in a previous state and then the master checks for DMA_RDY_TH0 and in the RD_CTRL state, the lines SLCS and SLOE are asserted as well as keeping the A0 asserted.

This is done to utilize the clock cycles to get the address stable and that's why the address line is asserted a state before the RD_CTRL state for the address line to get stabilized before the slave starts sampling that line.

In the method you proposed:

                                   RD_WR_IDLE--(if FLAGA & &DMA_RDY_TH0)-->DR_ADDR--(if true)-->RD_CTRL

There may be an issue with the address line not being stable and the slave tries to sample the address line, this may make the state machine behave uncertainly.

Also, in the above transition equation, what would be the condition from DR_ADDR to RD_CTRL? The DR_ADDR--(if true)-->RD_CTRL condition that would be replaced in place of "if true"?

Regards,

Yashwant

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YashwantK_46
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Hello,

As mentioned in the AppNote An87216, this implementation in the state machine is correct:

                             RD_WR_IDLE--(if FLAGA)-->DR_ADDR--(if FLAGA & &DMA_RDY_TH0)-->RD_CTRL

The explanation for the same is given in the appnote as follows:

    The master state machine moves from the RD_WR_IDLE state to the DR_ADDR state when there is some data on the slave side DMA buffer. In this state, the master drives the address lines. A0 is driven HIGH to address thread 1 of slave FX3. Then it checks if there is any free buffer and moves to the RD_CTRL state based on DMA buffer availability. In this state, the master drives the address and control signals SLCS# and SLOE#.

As mentioned, the master will firstly check for any data on the slave side, if there is any data (FLAGA asserted), master driver the thread address (using A0, A1) and then checks for any internal buffers.

Please read through section 4.2 Synchronous Slave FIFO Read Sequence on Page No. 7 of the appnote to get a complete understanding of the read sequence.

Regards,

Yashwant

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WGT_4383351
Level 5
Level 5
First like received

Yes, but the second way could also work:

If there is data in slave and there is free buffer in master, then go into the read state chains.

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Hello,

As shown in the slave read sequence,

pastedImage_0.png

The flow in the GPIF II designer:

                                   RD_WR_IDLE--(if FLAGA)-->DR_ADDR--(if FLAGA & &DMA_RDY_TH0)-->RD_CTRL

As soon as FLAGA is asserted, the address line A0 is asserted in a previous state and then the master checks for DMA_RDY_TH0 and in the RD_CTRL state, the lines SLCS and SLOE are asserted as well as keeping the A0 asserted.

This is done to utilize the clock cycles to get the address stable and that's why the address line is asserted a state before the RD_CTRL state for the address line to get stabilized before the slave starts sampling that line.

In the method you proposed:

                                   RD_WR_IDLE--(if FLAGA & &DMA_RDY_TH0)-->DR_ADDR--(if true)-->RD_CTRL

There may be an issue with the address line not being stable and the slave tries to sample the address line, this may make the state machine behave uncertainly.

Also, in the above transition equation, what would be the condition from DR_ADDR to RD_CTRL? The DR_ADDR--(if true)-->RD_CTRL condition that would be replaced in place of "if true"?

Regards,

Yashwant

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WGT_4383351
Level 5
Level 5
First like received

Why my method may make the address unstable? My method is first address then ctrl, the same with the original method, the difference is only where to check the condition to go into read states.

if true means LOGIC_ONE.

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Hello,


According to the method, RD_WR_IDLE--(if FLAGA & &DMA_RDY_TH0)-->DR_ADDR--(if true)-->RD_CTRL

As soon as the slave signals the master that it has some data by asserting FLAGA, the master will check if there is any internal buffers available and as soon as there is enough buffer available in the master, it will drive the address lines then and as soon as the address lines are pulled, the state machine will jump to the next state since there is no transition equation ( if true ) and this may have either the address lines not being pulled for enough time or the DR_ADDR state taking more time and waiting until the address lines are stable.

If the address lines are not stable by the time the slave starts sampling data, the behaviour cannot be determined and is not known to us.

The current implementation of the state machine drives the address lines as soon as FLAGA is asserted by slave so that the un-utilitzed clock cycles are used in the master state machine and then against checks for FLAGA and available free buffers and then goes to RD_CTRL state.

You can go ahead and try the transition equation that you proposed, but since we don't have any information on it or tried, i can't comment about the behavior of the master state machine.

Regards,

Yashwant

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