Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

USB superspeed peripherals

JaYe_3798301
Level 2
Level 2

Hi,

I have a question towards the SLWR and SLCS timing in the master side GPIFII interface.

In Figure 6. of the AN82716, the SLCS signal becomes low and then the SLWR signal becomes low.

I've also attached the snapshot of the figure in attachment.

The timing diagram of the GPIFII designer project of the master side shows the SLWR comes low before the SLCS signal.

Please see the attached master_gpif2_designer file.

Is there anything I misunderstand?

Thanks,

Jay

0 Likes
1 Solution
YashwantK_46
Moderator
Moderator 100 solutions authored 50 solutions authored 50 likes received
Moderator

Hi,

There is a parameter in the GPIF Designer : OUTPUT VALUE which affects the way in which a GPIO is asserted and when it is shown as asserted.

So, if a GPIO is configured as EARLY, there is a latency of 2 clock cycles for it to show in the timing diagram from the point it is asserted,

And, if a GPIO is configured as DELAYED, there is a latency of 3 clock for it to show from the moment it is asserted in the state machine.

In the master state machine, SLWR is early and SLCS is delayed, and hence there is a difference in the timing diagram as you have observed.


Please refer to the document :

C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc\GPIFII_Designer\gpif2_designer_userguide.pdf for more insight into the configuration

Regards,
Yashwant

View solution in original post

0 Likes
5 Replies
YashwantK_46
Moderator
Moderator 100 solutions authored 50 solutions authored 50 likes received
Moderator

Hi Jay,

The timing diagram shown in appnote AN87216 is the correct one.

Please don't refer to the timing diagram of the GPIF designer project as it is not accurate.

Regards,

Yashwant

0 Likes
JaYe_3798301
Level 2
Level 2

Hi,

I also use a logic analyzer to measure the signal on my development board, the measurement picture is attached.

The SLWR also comes low before SLCS.

I use the original design files and projects downloaded without any changes.

Does that mean the example projects do not follow the application note?

0 Likes
YashwantK_46
Moderator
Moderator 100 solutions authored 50 solutions authored 50 likes received
Moderator

Hi,

There is a parameter in the GPIF Designer : OUTPUT VALUE which affects the way in which a GPIO is asserted and when it is shown as asserted.

So, if a GPIO is configured as EARLY, there is a latency of 2 clock cycles for it to show in the timing diagram from the point it is asserted,

And, if a GPIO is configured as DELAYED, there is a latency of 3 clock for it to show from the moment it is asserted in the state machine.

In the master state machine, SLWR is early and SLCS is delayed, and hence there is a difference in the timing diagram as you have observed.


Please refer to the document :

C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc\GPIFII_Designer\gpif2_designer_userguide.pdf for more insight into the configuration

Regards,
Yashwant

0 Likes
JaYe_3798301
Level 2
Level 2

Hi,

Thanks for your explanation.

If I would like to use a FPGA to replace master FX3 and keep the slave Fx3, should my FPGA follow the timing diagram on the application note or follow the timing on the GPIF designer and measured data?

0 Likes
YashwantK_46
Moderator
Moderator 100 solutions authored 50 solutions authored 50 likes received
Moderator

Hi Jay,

The FPGA should follow the timing diagram from the application note as it explains the timing according to which the slave functions ( read/write ) depend upon and should be taken care by the master.

Regards,

Yashwant

0 Likes