AN65974 State Machine

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NiTo_4448151
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Can someone explain how single state machine given (syncslave_fifo) in GPIF II project folder in AN65974 corresponds to state machines shown in Application Note for all the examples

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Rashi_Vatsa
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Hello Nitya,

The state machine in the GPIF II folder is will be running on the FX3's  GPIF II (slave) interface.

The state machines explained in the application note describes four transfer modes are Loopback, Short Packet (Partial), Zero-length Packet, Stream IN, and Stream OUT transfers, for the implementation of state machine on FPGA (master). For different modes, the state machine designed (which will be running on FPGA), is explained in the sub sections of 11.4

fpga.PNG

The FPGA state machine will switch between these modes based on the status of the switch (on the SPARTAN 6 board - Xilinx SP601 DVK board).

fpga_1.PNG

Please let me know if any queries on this

Regards,

Rashi

Regards,
Rashi

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Rashi_Vatsa
Moderator
Moderator
Moderator
5 likes given 500 solutions authored 1000 replies posted

Hello Nitya,

The state machine in the GPIF II folder is will be running on the FX3's  GPIF II (slave) interface.

The state machines explained in the application note describes four transfer modes are Loopback, Short Packet (Partial), Zero-length Packet, Stream IN, and Stream OUT transfers, for the implementation of state machine on FPGA (master). For different modes, the state machine designed (which will be running on FPGA), is explained in the sub sections of 11.4

fpga.PNG

The FPGA state machine will switch between these modes based on the status of the switch (on the SPARTAN 6 board - Xilinx SP601 DVK board).

fpga_1.PNG

Please let me know if any queries on this

Regards,

Rashi

Regards,
Rashi
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Hi Rashi,

I'm using Altera Cyclone board, in that case can you explain the state machine in the GPIF II folder that is  running on the FX3's  GPIF II (slave) interface as explained in AN87216 (Designing a GPIF™ II Master Interface).

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Hello Nitya,

The state machine running on the slave (in both the application notes AN 65974 and AN 87216) are same.

slave_fifo.PNG

The status of the interfacing signals (FPGA - GPIF II) decide the state. At first, the address lines (Socket address (IN_ADDR)) are sampled to switch to appropriate socket. The interfacing signals are active low. As per signals from FPGA (read/write) the state machine will transition to appropriate state (as per the read and write sequence mentioned in section 5 of AN65974).

In write state IN_DATA will read the data coming from FPGA  and fill the DMA buffers. The DMA buffer will be committed to the consumer socket when is fully filled. this taken care in the firmware (dma call back)

In read sate the DR_DATA will drive the data coming from the producer socket (USB in this case) to the GPIF II data lines.

ZLP state will commit the zero length packet (DMA buffer without data is committed to Consumer socket

SHORT_PKT state when PKTEND is asserted low (before the DMA buffer is fully filled) the partially filled buffer is committed in this state

The flags A, B, C, D reflects the status of the DMA buffers (please refer to AN 65974)

Please let me know if any queries on this

Regards,

Rashi

Regards,
Rashi
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