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USB superspeed peripherals Forum Discussions

TzCh_3504586
Level 3
Level 3
5 likes given First like given

Hi, I have an AR0233 streaming 1920x1080p60 in RAW12 format.

I can see the MIPI receiver is capturing data, but the frame size is inconsistent, and there're no data coming through UVC to host.

I've tested with different PHY time delay (0x0A ~ 0x0F), the receiving frame size is not consistent for these tests as well.

The Frm_Sz should be 1920 * 1080 * 12 / 8 = 3110400 B

UART debug message:

Prod = 82 Cons = 81  Prtl_Sz = 16144 Frm_Cnt = 53 Frm_Sz = 3035056 B

TimeDiff = -1 ms FPS = 0

0 0 0 0 0 0 0 0 0

Prod = 82 Cons = 81  Prtl_Sz = 12864 Frm_Cnt = 203 Frm_Sz = 3031776 B

TimeDiff = -2 ms FPS = 0

0 0 0 0 0 0 0 0 0

Prod = 82 Cons = 81  Prtl_Sz = 15904 Frm_Cnt = 353 Frm_Sz = 3034816 B

TimeDiff = -2 ms FPS = 0

0 0 0 0 0 0 0 0 0

Prod = 82 Cons = 81  Prtl_Sz = 11776 Frm_Cnt = 503 Frm_Sz = 3030688 B

TimeDiff = -1 ms FPS = 0

0 0 0 0 0 0 0 0 0

Prod = 81 Cons = 81  Prtl_Sz = 30704 Frm_Cnt = 558 Frm_Sz = 3012800 B

TimeDiff = -1 ms FPS = 0

0 0 0 0 0 0 0 0 0

The sensor setting I use:

Untitled.png

/* AR0233_RAW12_1080p :  */

CyU3PMipicsiCfg_t AR0233_RAW12_1080p = 

{

    CY_U3P_CSI_DF_RAW12,  /* CyU3PMipicsiDataFormat_t dataFormat */

    4,                          /* uint8_t numDataLanes */

    1, /* uint8_t pllPrd */

    79, /* uint16_t pllFbd */

    CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */ 

    CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */

    CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t parClkDiv */

    0,                 /* uint16_t mClkCtl */

    CY_U3P_CSI_PLL_CLK_DIV_2, /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */

    1920,         /* uint16_t hResolution */

    0                         /* uint16_t fifoDelay */

};

/* GUID, globally unique identifier used to identify streaming-encoding format*/

    0X55,0X59,0X56,0X59,

0X00,0X00,0X10,0X00,

0X80,0X00,0X00,0XAA,

0X00,0X38,0X9B,0X71,

    0x10,                               /* Number of bits per pixel: 16*/

    0x01,                               /* Optimum Frame Index for this stream: 1 (1080p) */

    0x00,                               /* X dimension of the picture aspect ratio; Non-interlaced */

    0x00,                               /* Y dimension of the pictuer aspect ratio: Non-interlaced */

    0x00,                               /* Interlace Flags: Progressive scanning, no interlace */

    0x00,                               /* duplication of the video stream restriction: 0 - no restriction */

    /* Class specific Uncompressed VS Frame Descriptor 1 - 1080p */

    0x1E,                               /* Descriptor size */

    CX3_CS_INTRFC_DESCR,                /* Descriptor type*/

    0x05,                               /* Subtype:  frame interface*/

    0x01,                               /* Frame Descriptor Index: 1 */

    0x00,                               /* No Still image capture method supported */

    0x80,0x07,                         /* Width in pixel:  1920 */

    0x38,0x04,                         /* Height in pixel: 1080 */

    0x00,0x80,0xc6,0x13,             /* Min bit rate (bits/s): 1920 x 1080 x No Of Bits per Pixel x FrameRate = 331776000 */

    0x00,0x80,0xc6,0x13,             /* Max bit rate (bits/s): Fixed rate so same as Min */

    0x00,0x48,0x3f,0x00,             /* Maximum video or still frame size in bytes(Deprecated): 1920 x 1080 x 2 */

    0x40,0x42,0x0f,0x00,             /* Default frame interval (in 100ns units): (1/30)x10^7 */

    0x01,                               /* Frame interval type : No of discrete intervals */

    0x40,0x42,0x0f,0x00,             /* Frame interval 3: Same as Default frame interval */

  

    /* Endpoint Descriptor for BULK Streaming Video Data */

    0x07,                               /* Descriptor size */

    CY_U3P_USB_ENDPNT_DESCR,            /* Endpoint Descriptor Type */

    CX3_EP_BULK_VIDEO,                  /* Endpoint address and description: EP 3 IN */

    CY_U3P_USB_EP_BULK,                 /* BULK End point */

    CX3_EP_BULK_VIDEO_PKT_SIZE_L,       /* CX3_EP_BULK_VIDEO_PKT_SIZE_L */

    CX3_EP_BULK_VIDEO_PKT_SIZE_H,       /* CX3_EP_BULK_VIDEO_PKT_SIZE_H */

    0x00,                               /* Servicing interval for data transfers */

    /* Super Speed Endpoint Companion Descriptor */

    0x06,                               /* Descriptor size */

    CY_U3P_SS_EP_COMPN_DESCR,           /* SS Endpoint Companion Descriptor Type */

    0x0F,                               /* Max number of packets per burst: 12 */

    0x00,                               /* Attribute: Streams not defined */

    0x00,                               /* No meaning for bulk */

    0x00

};

/* UVC Probe Control Settings */

uint8_t glProbeCtrl[CX3_UVC_MAX_PROBE_SETTING] = {

    0x00, 0x00,                         /* bmHint : No fixed parameters */

    0x01,                               /* Use 1st Video format index */

    0x01,                               /* Use 1st Video frame index */

    0x0A, 0x8B, 0x02, 0x00,             /* Desired frame interval in 100ns */

    0x00, 0x00,                         /* Key frame rate in key frame/video frame units */

    0x00, 0x00,                         /* PFrame rate in PFrame / key frame units */

    0x00, 0x00,                         /* Compression quality control */

    0x00, 0x00,                         /* Window size for average bit rate */

    0x00, 0x00,                         /* Internal video streaming i/f latency in ms */

    0x00, 0x48, 0x3F, 0x00,             /* Max video frame size in bytes */

#ifdef CX3_UVC_1_0_SUPPORT

    0x00, 0x90, 0x00, 0x00              /* No. of bytes device can rx in single payload: 32KB */

#else

    /* UVC 1.1 Probe Control has additional fields from UVC 1.0 */

    0x00, 0x90, 0x00, 0x00,             /* No. of bytes device can rx in single payload: 32KB */

    0x00, 0x60, 0xE3, 0x16,             /* Device Clock */

    0x00,                               /* Framing Information - Ignored for uncompressed format*/

    0x00,                               /* Preferred payload format version */

    0x00,                               /* Minimum payload format version */

    0x00                                /* Maximum payload format version */

#endif

};

0 Likes
1 Solution

Use a workaround to solve this problem now.

I cropped the input size to 1280x1080p60 RAW12 and the video capture pipeline is working fine now.

But would still like to know why did the 1920x1080p60 RAW12 not working ?

The limitation for CX3 MIPI receiver board is 2.4Gbps total and 1Gbps per lane.

And 1920x1080p60 RAW12 runs in 300MHz CSI clk should be theoretically okay.

And another question is when I'm trying to configure the MIPI configuration, the SDK pops error when I'm trying to adjust CX3 MIPI Interface Configuration Output Pixel Clock over 100Mhz.

Shouldn't the limitation for Output Pixel Clock is 125Mhz?

Thanks,

Ping

View solution in original post

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6 Replies
YashwantK_46
Moderator
Moderator
Moderator
100 solutions authored 50 solutions authored 50 likes received

Hi,

Can you please probe the HV, LV and PCLK test points and share the traces?

Regards,

Yashwant

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Hi Yashwant,

Vsync and Hsync had been toggle, but looks unstable (synchronization signal is shifting)

Also one correction to the frame size, it should be 1920 * 1080 * 16/8 = 4147200 B since it's RAW12 in 16 bit package.

Hsync vs PCLK

imageFile.bmp

Vsync vs Hsync

imageFile.bmp

Best,

Ping

0 Likes

Hi Ping,

Can you please check for the number of full buffers that you can get in each frame?

Also, do you see any "commit buffer failure error"?

Can you please share your firmware?

Regards,

Yashwant

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TzCh_3504586
Level 3
Level 3
5 likes given First like given

Hi Yashwant,

If I capture the data for a while, UART print out will indicate dma_reset_flag == 1. and sometimes it'll print "CB failure" indicating dma_reset_flag == 0.

Other than these I didn't see any commit buffer failure error.

I attached my working source and firmware I'm using for your reference.

Firmware name: "Cx3UvcAS0260"

UART Print:

Prod = 85 Cons = 84  Prtl_Sz = 13184 Frm_Cnt = 23329 Frm_Sz = 3142544 B

TimeDiff = -1 ms FPS = 0

0 0 0 0 0 0 0 0 0

Prod = 85 Cons = 85  Prtl_Sz = 20016 Frm_Cnt = 23626 Frm_Sz = 3149376 B

TimeDiff = -1 ms FPS = 0

0 0 0 0 0 0 0 0 0

Prod = 85 Cons = 84  Prtl_Sz = 15952 Frm_Cnt = 23921 Frm_Sz = 3145312 B

TimeDiff = -1 ms FPS = 0

0 0 0 0 0 0 0 0 0

Prod = 85 Cons = 84  Prtl_Sz = 12128 Frm_Cnt = 24218 Frm_Sz = 3141488 B

TimeDiff = -1 ms FPS = 0

0 0 0 0 0 0 0 0 0

Prod = 85 Cons = 84  Prtl_Sz = 12080 Frm_Cnt = 24515 Frm_Sz = 3141440 B

TimeDiff = -1 ms FPS = 0

0 0 0 0 0 0 0 0 0

Prod = 85 Cons = 84  Prtl_Sz = 4480 Frm_Cnt = 24815 Frm_Sz = 3133840 B

TimeDiff = -2 ms FPS = 0

0 0 0 0 0 0 0 0 0

Prod = 85 Cons = 84  Prtl_Sz = 704 Frm_Cnt = 25111 Frm_Sz = 3130064 B

TimeDiff = -1 ms FPS = 0

0 0 0 0 0 0 0 0 0

Prod = 85 Cons = 84  Prtl_Sz = 8176 Frm_Cnt = 25404 Frm_Sz = 3137536 B

TimeDiff = -1 ms FPS = 0

0 0 0 0 0 0 0 0 0

Video timer

0 0 0 0 0 0 0 0 0

Mipicsi Block status = 0x1

Prod = 84 Cons = 84  Prtl_Sz = 28192 Frm_Cnt = 25681 Frm_Sz = 3120736 B

TimeDiff = -1 ms FPS = 0

Thanks,

Ping

0 Likes

Use a workaround to solve this problem now.

I cropped the input size to 1280x1080p60 RAW12 and the video capture pipeline is working fine now.

But would still like to know why did the 1920x1080p60 RAW12 not working ?

The limitation for CX3 MIPI receiver board is 2.4Gbps total and 1Gbps per lane.

And 1920x1080p60 RAW12 runs in 300MHz CSI clk should be theoretically okay.

And another question is when I'm trying to configure the MIPI configuration, the SDK pops error when I'm trying to adjust CX3 MIPI Interface Configuration Output Pixel Clock over 100Mhz.

Shouldn't the limitation for Output Pixel Clock is 125Mhz?

Thanks,

Ping

0 Likes

Hi Ping,


Can you please take Wireshark traces for the 1920x1080p60 RAW12 and share them with me?

It would help me figure out what is going wrong in that case.

-And another question is when I'm trying to configure the MIPI configuration, the SDK pops error when I'm trying to adjust CX3 MIPI Interface Configuration Output Pixel Clock over 100Mhz.

Shouldn't the limitation for Output Pixel Clock is 125Mhz?

>>> Though the theoretical limitation of the pixel clock is 125 MHz, the SDK tool is congfigured not to allow the Output Pixel Clock to exceed over 100MHz and it is advised to be in the 100MHz clock range.

Regard

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